IPC-D-782 says, "Nonfunctional lands should be included on internal layers
for all plated-through holes.  Nonfunctional lands need not be used where
electrical clearance requirements do not permit, such as ground planes,
voltage planes and thermal planes."

Norman Einarson's Bare Board PWB Design Manual says, "Non-functional lands
should be removed from inner layers, prior to the artworks being released
for production.  These are the lands on inner layers where no circuit will
be connected to any hole."  Further, its says, "During the lamination
process, the epoxy in the pre-preg material will flow to the outer edges of
the board.  This may cause the lands with no traces attached to float when
the epoxy is flowing prior to cure."

Summary - Talk to your own PCB vendor.

-----Original Message-----
From: KELLY M SCHRIVER <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Monday, December 14, 1998 2:48 PM
Subject: Re: [DC] Plated Thru pads


>Scott -
>
>I think most of us are leaving all of the unused pads in place on plated
thru
>holes and vias, unless removal is necessary to increase routing density.
>Leaving the pad stack intact adds just a bit of  uniformity and stability
to
>the hole.   With part of the pads gone, Z axis attachment of the barrel can
>vary considerably.  This gets more important as the hole aspect ratio
>increases.
>
>ITRI recently completed some testing dealing with allowable
misregistration,
>which strongly supports the stability theory.  This testing suggests that a
>trace connecting directly to a barrel will survive IF a pad is present,
even
>though severely misregistered (giving a breakout condition).
>
>Regards - Kelly
>
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