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October 1998

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Subject:
From:
David Ratte <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Mon, 5 Oct 1998 19:10:25 -0400
Content-Type:
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text/plain (120 lines)
First of all, I know this is a dead document, but since you were looking for anything that addresses this issue, paragraph 4.23.3.1 of MIL-STD-2000A specifically addresses stacking of chips: (page 16)

4.23.3.1 Stacking of Chips. Chip devices shall be mounted only to printed wiring or parts specifically configured to receive them (see figure 7).

Since I don't have my scanner on, I'll tell you that figure 7 shows a couple of configurations of stacked 1206 resistors with the words UNACCEPTABLE DESIGN beneath them.

I'm sure that there is probably something in IPC-610 about it too but I don't have a copy of that handy.

-Dave Ratte
[log in to unmask]

----------
From:  Paul Klasek [SMTP:[log in to unmask]]
Sent:  Monday, October 05, 1998 6:50 PM
To:  [log in to unmask]
Subject:  Re: [TN] ASSY: stacking 1206 chip resistors

Hi Sherman ;
This may be not the answer you seek ; so : "believe it or not" :
There are few relatively bizarre practices ; but I'd say whole SMT
progress is from first glance :
resistors venting heat standing on side are prescribed quite often ;
as the reliability guys here often said the less (up to a limit) solder
the more reliable the joint (visible in new cap pad footprints) .
Not that I'd find res. hooked on corners particularly appealing from a
lot of other views ; but they live

On your subject :
I did the same (stacking) in telecom application in past (drop tests;
vibrating at "railway" frequencies >you name it [calibration mainly) ;
and still here in R&D runs ;
as long as you have the heat dissipation (bit impeded in bottom two)
under control and smear the paste sideways without much mess you have no
problem . 1206 metalisation is actually asking for it (fairly "rich") ,
very robust standard pads will have no problem holding 3 stack .

As long as he's got the track to cope with the stack ; he's in the
obviously constrained design situation making sense to me .

PS
You won't find this specific "rules" . Rules, generally, are something
to quiz constantly anyhow, for a lot of reasons
PPS
If you handle them in post reflow assy (like calibrations) try to use
paste and fine heat jet (with thermocoupler on hand first time) ;
the bugs will get less shocked than with the traditional wire &
overblasted tip . Hold the stack with needle from top (drop arm) .

See you
Paul Klasek
http://www.resmed.com

> ----------
> From:         Sherman Banks[SMTP:[log in to unmask]]
> Sent:         Tuesday, 6 October 1998 6:54
> To:   [log in to unmask]
> Subject:      [TN] ASSY: stacking 1206 chip resistors
>
> Hi Folks,
>
> We've got an engineer who wants to stack 1206 resistors 3 high in
> order to
> achieve a larger power rating. While it is intuitively obvious to us
> that
> this is NOT the way to go, we are at a loss to find any published
> documents
> that caution or forbid the practice.
>
> Can anyone cite a published source that can give more specific "rules
> or
> guidelines" on this subject.
>
> We've searched, J-STD-001, SM-780, SM-782, A-610, and R-700
>
> Help!!!!!
>
> REGARDS
> Sherman Banks
> [log in to unmask]
> 408/481-6047
>
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