Depending on how much vacuum your test stand generates, you may be able to
do what I have done in the past, that being: Use very small vias under those
lo-profile and/or larg footprint parts and paste only those vias that remain
clear of components.  Another option, make all your signal interstitial vias
small, keep your power and ground conects larger and just paste those to
seal them. By small, I mean on the order of .010-.015 finished size nominal
and call out something like .000-.015 for the range.  For power/gnd either
use the same small size redundantly or use a .020-.028 range via that you
would plug.  Lastly, I obviously don't know what size your board is or the
number of vias you'll be using - but, you may be able to get aeay without
plugging them at all.  Anytime a component body can rest on the paste,
you're asking for trouble.  Better off avoiding that senerio.  Good luck.
Russ

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Todd Vorpahl
Sent: Thursday, October 29, 1998 1:02 PM
To: [log in to unmask]
Subject: [TN] top side solderpaste


Hi all,

For SMT double-sided boards we will typically solderpaste all vias on the
bottom
side for vacuum test reasons.  For a single-sided SMT board, it makes sense
to
do this on the top side (costly to create another stencil just to paste vias
on
the bottom side).

My question is this....we have a prototype that has several vias located
beneath
some pretty low profile TSOPs, where the body is 2-8 mils off the board.
I've
come to understand that a 6-8 mil solder print is typical.  Has anyone
experienced shorting of vias beneath low profile parts due to the paste?

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