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October 1998

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From:
James Kittel <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Thu, 22 Oct 1998 06:45:25 -0600
Content-Type:
text/plain
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text/plain (125 lines)
Has anyone really done any testing and verified these actions allow a
PWB to be stored longer and remain solderable.  My experience is that
most of my solderability problems were related to the type of surface
finish used and base metal migration.  Surface oxidation or
contamination was never a problem I encountered.

>-----Original Message-----
>From:  Carl Levoguer [SMTP:[log in to unmask]]
>Sent:  Thursday, October 22, 1998 2:42 AM
>To:    [log in to unmask]
>Subject:       Re: [TN] Shelf Life/Storage for Bare PCB
>
>As a matter of interest, what kind of paper do you use?
>I would guess shiny is better than matt finish for example to stop
>particulate contamination of the surface.
>Also I would have thought (I may be wrong) that bleached paper may
>contain halide ions for example.
>
>I have interest in this area as I need to store ~500 boards after
>cleaning for SIR testing.
>The boards must be and stay v. clean.
>Any hints or tips greatly appreciated.
>
>Regards
>
>Carl.
>
>>>Reply to your message of 21/10/98 23:47
>>We're getting them interleaved with paper and sealed ;
>>Found that even better than just stacking them up with desiccant ; for
>>few reasons .
>>The desiccant and indicators have usually  too localized effectiveness
>;
>>
>>that's why Jim keeps the qty so low .
>>The ESD bag is indeed a luxury ; but I suppose he's got a reason for it
>>.
>>To keep segments (ground?) of copper from picking up a charge, Jim ? .
>>Did you measure it ; traced it ; or is it just one of the safe theories
>>?
>>For us with paper insulation and only the edge (insulated) contact we
>>skipped it .
>>Wrong ?
>>
>>> ----------
>>> From:         Jim Marsico 516-595-5879[SMTP:[log in to unmask]]
>>> Sent:         Thursday, 22 October 1998 3:12
>>> To:   [log in to unmask]
>>> Subject:      Re: [TN] Shelf Life/Storage for Bare PCB
>>>
>>> We require that all boards are individually wrapped in tarnish
>>> inhibiting
>>> paper, and placed in a sealed ESD bag with a humidity indicator and
>>> desiccant.
>>> (No more than 10 PWBs per bag.)
>>>
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>>
>>>End of message
>
>Dr. Carl Levoguer
>CMMT
>National Physical Laboratory
>Queens Rd, Teddington, Middlesex.
>TW11 0LW
>Direct Line : +44 181 943 6263
>Fax: +44 181 943 6453
>
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