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October 1998

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Subject:
Reg: Voids in Solder Bumps
From:
Manish <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Tue, 20 Oct 1998 09:57:02 -0400
Content-Type:
TEXT/PLAIN
Parts/Attachments:
TEXT/PLAIN (29 lines) 
Hi Everybody

I work for a company that fabricates flip chip by electroplating.  We do
some of the prototype assembly in house.  We do observe substantial voids
in the solder bumps after reflow.

I have tried reflowing the same chips on copper (instead of the laminate).
I placed feeler gauges under the dice in order to limit the collapse of
the solder bumps.  With the same flux and the reflow profile very few
voids were observed for the dice placed on copper.

Could anybody please help me with this issue. Any suggestions would be
highly appreciated.

Regards
Manish

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