I think you will find it was DEC Canada where it started.  The company is
PWB Interconnect Solutions in Ottawa, Ontario.  The contact is Bill Birch e
mail:  [log in to unmask]  The IPC has groups  working on the
correlation of IST to Thermal ovens and other testing methods.  There is a
positive correlation between both the oven/IST/delco 1000 hour test  that
was presented in a working session at IPC expo. It also is a good way using
coupons to both on line process check for post separation and to evaluate
coupons from boards to see if the board itself will have interconnect post
separation.  There is even a draft of a TM-650 test method in work.   I got
a summary of the technology some time ago, off the web at
http://ww3.sympatico.ca/gerard.gavel/ist.htm, and you might want to try that
site.

Anyone who has had a board interconnect open up can appreciate the value of
this test method.  The post separation task group next meets at IPC/SMTA
Expo on October 28 8-10AM.  That is followed by the Plated Through Via
Reliability Accelerated Test Methods group at 10:15-12:00 lead by none other
than Bill Birch.
 ----------
From: Bev Christian
To: [log in to unmask]
Subject: Re: [TN] ICT for bare boards
Date: Wednesday, October 14, 1998 11:54AM

Doug,
It is an electrical power cycling test invented by someone at Nortel, if I
am not mistaken, sometime in the 80's.  The technology was sold off to a
little stand-alone company in Ottawa, Ontario.  Where it went after that, I
do not know.  I know that Via Systems Canada (the old Circo Craft) have a
set up.

Essentially a thermal stress is applied by resistance heating an array of
PTH's.  Coupons are cycled until failure occurs.   These results have been
correlated with the pass/fail criteria of the thermal shock test in
MIL-P-55110C.  You can get results in about 20 hours, rather than 1000's of
cycles that take some large fraction of an hour each.  That's all I know.

Good luck,
Bev Christian
Nortel

> ----------
> From:         Doug Jeffery[SMTP:[log in to unmask]]
> Sent:         Wednesday, October 14, 1998 9:01 AM
> To:   [log in to unmask]
> Subject:      [TN] ICT for bare boards
>
> Technet,
>
> Has anyone heard of "ICT for bareboards and what does it stand for?
>
> Recently this testing techneque was laid on one of my sales reps.  I
> thought they were referring to ICT or in circuit testing done at the
> assembly level. He insists that they were referring to bare board
> testing beyond opens and shorts.
>
> Does anyone know of this testing and where I can find information about
> it?
>
> .
>
> Douglas C. Jeffery
> Pre-Production Engineering Manager
> Electrotek, Inc.
> PH: 414-762-1390
> Fax: 414-762-1510
> Email: [log in to unmask]
>
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