Good Morning Bob,
I think you and I spoke in the past concerning PWB/heatsink assemblies built
at the "old" North American Printed Circuits. Back in those Norden days,
when Gary Cormack was screaming at us for late deliveries, you may have
spoken with Bill Moorhouse and myself on any number of issues concerning
heatsinks. The heatsink facility is now located in a 12,000 s.f. addition
alongside Tyco's backplanes facility. I happened to read your TechNet
letter and saw references to heatsink design in your survey. Please feel
free to contact me on any design or manufacturing issues concerning heatsink
technology. I'm not sure what you're specifically looking for at this time,
so I look forward to hearing from you with any questions. Talk to you soon.
Have a good day. Thank you.
Ken D'Angelo
Tyco Value Added Systems Div.
T: 860.684.8000, ext. 4332
F: 860.684.0714
-----Original Message-----
From: Vanech, Bob [SMTP:[log in to unmask]]
Sent: Wednesday, October 14, 1998 10:38 AM
To: [log in to unmask]
Subject: [TN] pwb design survey
I think that we have fixed the formatting problem experienced last
week with this survey. So, I am resubmitting it again to the forum. Thanks.
Bob Vanech
****************************************************************************
******************
> To all...
>
> A few days ago, we had a lot of activity related to pwb
design > cycle/requirements. > I've been having an ongoing battle with
those, that have no idea what we > do, but > are experts in what we do, you
all know what I mean. I keep hearing that > "These types of designs are
completed much quicker and cheaper by other > companies? Why can't you be
competitive?" When I question them on their > source of information, it's
usually, "My project buddy at Company ABC said > so?" > When I ask for the
details, such as size of board, number of layers, > technologies, > etc., it
becomes very evident that we are comparing apples to bananas, > pears to >
grapes, you know where we're going with this. When I talk to my >
counterparts or > the "designers in the trenches", I hear that they are
experiencing similar >
> comparisons in their workplace. So, it seems as if we are
trying to > justify our > hours and calendar time against a nonexistent
target...Great for the > bean-counters > that are kicking the c##p out of
us, but not really fair to the guys/gals
> doing the > REAL work.
>
> Sooooo, maybe it's time to get together and collect some
HARD, REAL data > on > what we do, so the next time the hot shots try to
blow smoke up our butts, > we'll > have facts, not fictions, to justify our
design cycle. I'm including a
> list of design > parameters, similar to those listed in
the e-mails, that will allow us to > INTELLIGENTLY > evaluate what it takes
to do a design. Obviously, this will not be true > for all designs, > but
at least it will give us a general idea of what we did, with what we > were
given, > what we outputted and what kind of time it took for a family of
SIMILAR
> designs.
>
> Of course, we might have those that will, as one
commented, toot toot toot > their > horn with some exaggeration. However,
if enough replies come in, one can > throw > out the high's and low's and go
with the average. At least it can be a > starting point.
>
> So, if you want to fill out the survey and send it
directly back to me, I > will try to put > it in a form that makes sense and
send it back to TechNet for all to > review. If I have > missed any real
important items, a subsequent survey can be initiated. If > this > works
and the net finds it helpful, then other families of surfaces can be >
surveyed.
> Thanks in advance!!
>
>
>
>
> NOTE:
> For this first cut, please only submit designs that are
between
> 9.3 x 6.7 (approx. VME) to 9.3 x 10.2
>
>
EXAMPLE YOUR
DESIGN
---------------
----------------------
> Classified/Board Class 3
> Type per IPC-2221/2222 /Type 5
>
> Size 9.25 x 10.18
>
> Type of Design Digital/TTL/ECL/SMT
> Thermal Constraints
>
> Number of Components
> Microcircuits 50
> Discretes 350
> Other Uniques None
>
> Type of Microcircuits 132&160&224 Pin
> Gate Arrays/24 Pin Quad
> Flatpacks/16 & 24 Pin
Flatpacks
>
> Type/Pin Count of 280 Pin SMT/2 @
> Connectors 20 Pin SMT
>
> No./Description of Layers 15 Total Layers
> Top/Bottom Comps/Pads/
> Signal (See Below)
> Critical 2 for TTL/2 for ECL
> Non-Critical Routed on TTL/ECL
> Planes 9
> Split Planes None
>
> No. of Pins/Nets 2250/420
>
> Trace/Space (Majority) .007/.0055
>
> % of Critical Routes 50%
>
> % of Routing Technique
> Manual 100%
> Autoroute None
>
> Avg. No. of Net List/ 4/3/5
> Placement/Routing
> Iterations after Rel.
>
>
>
>> Type of Routing o Impedance
> o Matched Lengths
> for True & Comps
> o Critical Hi-Sp Clks
> o Termination Res.
> on all diff. pairs
> o Min. ECL/TTL Shadowing
> on all layers
> o Min. Crosstalk
> o Stitching of Ground
> Planes to Reduce
> Return Current Path
>
> Tasks Included in o Generate Land Patterns
> Design Cycle o Gen. Parts List from
> Elec. Schematic
> o Gen. Placement from
> Elec. Prelim. Layout
> o Gen. Thermal Data
> o Route Crit. Signal/
> Review by Elec./Reroute
> as required
> o Same as above for
> remaining routes
> o Gen. DXF Files to
> Dft. for PWB/ASSY Dwgs
> o Gen. Gerber files for
> Phototooling
> o Check PWB Dwg vs. Film
> o Check ASSY Dwg vs. PL
> o Gen. Cam Aids
> o Rel all Dwgs/Files to
> Config. Management
>
> Design Cycle (Working Days) 90
>
> Cal. Time - Including Changes 130
> in Rel. Data/Checking/Review-
> ing by Outside Disciplines/Stop
> Work by Project Orders
>
> Comments o Changes from top
> H'sink to Backplate
> o Stopped Work/2 months
> Final Pin Outs of 132A
> Not Defined from Vendor
>
**************************************************************************
> ****************************
>
> Complete if you off-load designs to design services:
>
> Data Give to Outside o Statement of Work
> Design Service o Critical Design
Ground
> Rules
> o Placed/Net List
>
> Data Received o Routed Electronic
> Data Base of all Files,
> Compatible to our Sys.
> o DXF files for Drafting or
> PWB/ASSY Dwgs. on
> our Format
>
> Days Saved by Off-Loading o Add 1-2 Weeks to Cycle
> to Design Service
>
>
>
>
>
>
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