Gary,

My personal understanding of white tin versus the age old "gray tin" is that white tin holds a different crystalline lattice structure making it more resistant to dendritic growth and temperature excursions.  This difference in crystalline structure also imparts a different appearance giving the name "white tin."

Typically the material is deposited after soldermask application, and any exposed white tin is thereby  for solder purposes only.  The shelf life without dendritic growth is as good if not better than many processes.  There could be other applications in the works for the material, but one needs to contact a manufacturer.

bottom line =>   white tin : gray tin :: diamond : carbon  (Would you rather have a diamond or carbon tipped saw blade?]

I understand there is a little misinformation floating around, though, because old memories are hard to break.

[This is an unpaid endorsement and personal opinion.]

Paul Wilson
Manager of R&D / Plant Chemist
Circuit Center, Inc.
[log in to unmask]



----------
> I don't know what "white" tin is, but pure tin coating could be a BIG problem.
> The slightest bit of moisture
> and dendrites grow like crazy at very low voltages (like 3 to 5 volts)!
> Better be sure everything is covered
> with soldermask or conformal coat.
>
> Gary P.
>
> Rick A. Scovel wrote:
>
> > I have the exact same situation - PCB manufactuer asking customers to
> convert
> > over to "Immersion White Tin"; Please let me know what you find - I will be

> > following your thread -
> >
> > Brian Rusten wrote:
> > >
> > > Dear Technettes
> > >
> > > One of our PCB Manufacturers has recently started using the "Omikron"
> > > (Immersion White Tin) process as an alternative to Hot Air Leveling.
> > > They are asking us (the designers) whether they can use it for our boards.
> > >
> > > I've looked through the archives, and there seem to be no major problems
> > > noted so far. Still, it's a couple of months since it's been discussed,
> > > and it is a new(ish) process. So, here goes :
> > >
> > > Does anyone know of any particular adverse design or assembly implications
> > > of using this process? Do you know (even as hearsay) of any problems with
> > > the process?
> > >
> > > Thanks, and Regards
> > >
> > > Brian Rusten
> > >
> > > Contract PCB Design Engineer
> > > JNA Telecommunications Ltd  Ph (02) 9935 5777      Fax (02) 9417 3862
> > > (Now "A Lucent Company")
> > >
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