What are the failure mechanisms for stacked chip components.  If heat
     dissipation is accounted for with stacking, then is it strictly stress
     relief at the solder joints?

     If it is stress relief at the solder joints, then why do IPC spec's
     allow such bulbous joints for parts that aren't stacked?

     Would the failure occur at the chip-to-board interface or at the
     chip-to-chip interface?  Has anyone actually found stacking to be a
     problem or is it more of a theoretical argument?

     We design RF systems and would like to stack chips (especially caps)
     for tuning purposes.

     Frank Hinojos

################################################################
TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c
################################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body:
To subscribe:   SUBSCRIBE TechNet <your full name>
To unsubscribe:   SIGNOFF TechNet 
################################################################
Please visit IPC's web site (http://www.ipc.org) "On-Line Services" section for additional information.
For technical support contact Hugo Scaramuzza at [log in to unmask] or 847-509-9700 ext.312
################################################################