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September 1998

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Subject:
From:
Lum Wee Mei <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Sat, 5 Sep 1998 10:55:27 +0800
Content-Type:
text/plain
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text/plain (71 lines)
I hope the following information can be of some help to you.

(1)    With reference to "Printed Circuit Handbook by Clyde F. Coombs Jr" :
Consider a 0.04" diameter hole plated to a 2-oz internal power plane with 0.001" minimum copper in the
hole. The copper hole wall is equivalent to:
    0.04" x 0.001" x PI = 125 x 10 exp -6 sq.in
At the interconnection to the power plane, there will be :
    0.04" x 0.0028" x PI = 352 x 10 exp -6 sq. in (Note : 0.0028" is the thickness of 2-oz copper)
With reference to the current-carrying capacity chart of MIL-STD-275 or now IPC-D-275, a 125 x 10 exp -6
sq. in conductor will carry approximately 2A with a 10 deg. C rise above ambient.

(2)    With reference to " Handbook of Printed Circuit Design, Manufacture, Components & Assembly by
Giovanni Leonida" :
I = (W/K) exp0.538 where the value of K =
3.60 for 1-oz/10 deg C above ambient        1.97 for 2-oz/10 deg C above ambient
1.97 for 1-oz/20 deg C above ambient        1.10 for 2-oz/20 deg C above ambient
1.45 for 1-oz/30 deg C above ambient        0.80 for 2-oz/30 deg C above ambient
1.20 for 1-oz/40 deg C above ambient        0.65 for 2-oz/40 deg C above ambient

1.30 for 3-oz/10 deg C above ambient
0.80 for 3-oz/20 deg C above ambient
0.53 for 3-oz/30 deg C above ambient
0.45 for 3-oz/40 deg C above ambient
W is the width of the conductor in mils.

Example : Current which can flow through a conductor with W = 0.15in, 3-oz/sq. ft at temperature rise of 40
deg C is
I = (150/0.45)exp0.538 = 333.3exp0.538 = 22.8A. Since the conductor width is more than 0.04", the value
obtained should be decreased by 50%.


Regards.


Scott Holthausen wrote:

> Hey TechNeter's
>
> Does anybody have an equation that could help a person determine the
> current handling capability of through hole vias?  Our practice has
> normally been to use multiple vias to connect components with high current
> paths to plane layers.  However, that isn't good enough for one of our
> engineers who wants more than an approximation, and wishes to find out
> whether we are putting more vias on the board than we need to.
>
> Thanks,
> Scott Holthausen
>
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