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September 1998

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Subject:
Re: Fab/Assy: Vias under chip components
From:
Jay Tsai <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Tue, 29 Sep 1998 14:49:08 -0700
Content-Type:
text/plain
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text/plain (52 lines) 
What kind of dry film soldermask do you intend to use?  You might want
to look at the thickness of the dry film soldermask. That might be a
concern.


On Tue, 29 Sep 1998 13:40:37 PDT
glenn pelkey <[log in to unmask]> wrote:

> Does anyone see a problem with placing a via under a chip capacitor?
> The via will be tented with dry film soldermask.  Assembly will be with
> epoxy or screened solder, reflow, and DI water clean.
>
> The potential for electrical shorts and remaining contaminates has us
> concerned.
>
> Thanks in advance for any input.
>
> Glenn Pelkey
> [log in to unmask]
> [log in to unmask]
> Maxtek Components Corp.
>
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Best Regards,
- Jay T. -

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