In a message dated 9/18/98 11:48:07 AM Pacific Daylight Time,
[log in to unmask] writes:

<< Electricity follows the path of least resistance.  This is true in an
electro-plating cell. When designers create a board that has dense areas and
areas with very isolated circuitry, the isolated circuits act like antennas in
the plating cell and they get more than their share of the plating.
When lines plate thicker than the rest of the board it is very hard to control
line width and spacing.  It is also dfficult to cover the high traces with
solder mask.

One approach has been to panel plate the copper.  After drill the panels are
electroless copper plated to activate the holes and then are plated
copper full thickness everywhere.  Then they are imaged and etched or imaged,
solderplated, resist stripped and etched.  Several problems with this approach
are; etching fine lines and spaces is impossible when the copper thickness is
too great and you waste a lot of copper plating the background areas that are
going to be etched off, and the panel plating is never as uniform in thickness
as you would like causing difficulty in etching uniform line widths accross
the panel.

Another approach has been to add thief to the areas where the circuits are
isolated.  There are computer programs that will automatically add
in dots or squares to any area that does not have conductors.  Usually the
size of the gap that has to exist before the dots are added is
adjustable.  If you have a concern about the thief cross-talking to your
circuitry or causing migration shorts, the answer may be to have the designer
use smaller dots for the thief and tell him they are not allowed within a
specified distance from the lines.  If you delete the thief completely you can
expect poor yields from the board shop with commensurate longer lead times and
higher costs. >>

Hi John!

     I just gotta' say, "You da' man!" What a great explaination behind
thieving! Even I understood it...and that's sayin' a LOT! Can I pick your
brain a little more? It's about panelization. From your experience, what is
usually the most common reason a panelized board fails bed of nails testing
and causes a circuit to be "X'ed-out" in a panel? Is there anything one can do
such as the thieving suggested to improve panel yields? There 's a few things
I know such as; smaller arrays yield better, and the less fine pitch the
better the yeilds, but I was wondering about the kinds of things that really
help the fab companies produce all good panels without "X-outs". I do
understand the view that a fab vendor kinda' takes it in the shorts when a bad
circuit is found in a panel when the customer wants all good ones, because
basically he has to toss a bunch of good boards away. But I was thinking that
if there were the kind of guidelines incorporated into a panel that really
makes it easy (or easier) for a fab vendor to produce 100% good panels might
make the price difference between good panels and ones that have "X-outs" a
little closer to each other.

It's been my experience that most buyers do not relate to the added expense
that occurs on the production floor when dealing with "X-outs"... they look
for the rock bottom price no matter what, and think they're doing a good job.
These are things such as having to go through each panel and put some sort of
machine recognizable mark at a consistent location on every "X'ed out" circuit
to utilize a bad board sensor on the pick and place machines. When you use
that function, that slows the throughput because the machines have to look at
every board before it starts doing anything. If you don't use that function,
then you've got to take the time to separate the panels into like
configurations as far as "X-outs" go, and then have separate placement
programs that match each configuration.

Solder paste usage is another. This may seem petty, but for instance at a past
company I worked for we built memory modules at very high volumes...during the
busy months it wasn't unusual for us to build 1,000,000 modules. Panel arrays
were anything from 10-up, to 22-up and they would allow different numbers for
the "X-outs" depending on how many circuits were on the panel. For instance on
the 10-ups they would allow 2, on the 22-ups they would allow 4...roughly 20%.
Each module could get printed with sometimes as much as a gram of paste
depending on whether it was double-sided or not, and over a busy month, that
winds up to be around 200,000 grams of paste down the ol' tubes (or in a
landfill)...at around .08 a gram that's $16,000!! Heck, that's a brand new
Ducati 916 and a brand new set of leathers every month!! (I have strange ways
of quantifying money figures...hehehe)

If you've got any tips that will help to increase panel yeilds would sure be
appreciated! I'd even let you take my "Duck" for a spin (when I get rich and
can buy one...GRIN)

-Steve Gregory-

################################################################
TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c
################################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body:
To subscribe:   SUBSCRIBE TechNet <your full name>
To unsubscribe:   SIGNOFF TechNet 
################################################################
Please visit IPC's web site (http://www.ipc.org) "On-Line Services" section for additional information.
For technical support contact Hugo Scaramuzza at [log in to unmask] or 847-509-9700 ext.312
################################################################