Hi Craig,
These are great questions that PCB manufacturers should be addressing
all over the world. I'll attempt to offer my thoughts.
* First, Yield, yield, yield... generally, narrower conductors and spaces,
smaller holes, thinner layers, albeit denser circuitization are more
challenging to manufacture and therefore have higher defect density
levels than designs with larger features built by the same manufacturer .
* Second, because of the miniaturization associated with smaller features,
greater lengths of conductor and spaces and greater numbers of holes
may be placed within the same area on a panel, the basic substrate
on which the boards are manufactured.
* Increased feature length and hole count per unit area, coupled with
higher defect density levels, translate into lower yields; much lower
when the manufacturer approaches the "knee of the curve."
* To take full advantage of miniaturization, tighter registration is
necessary, another factor leading to lower yields.
* To participate in the "leading-edge" market, a PCB manufacturer must
invest in new materials, equipment, processes - the latest technology -
along with a highly trained engineering staff to raise yields to
acceptable levels.
* Clearly, the downward pressure on yields and increased investments
associated with denser circuits serve to increase the cost to the
manufacturer.
* There is a wide range in capability and quality among the PCB suppliers
who serve the OEM market. Please refer to the column "Between The
Conductors" published in CircuiTree magazine. The April through
September, 1998 issues discuss supplier qualification and show
quantitative data for innerlayer and outerlayer conductor and space
yield and uniformity, via yield and uniformity, and registration
capability. Copies of these columns are available from the web at
http://biz.swcp.com/cat
Also available from the same web site is an example supplier
qualification summary report.
I trust that these general comments may be of help to you. If you desire
to investigate the capability of your current PCB supplier base, or
prospective suppliers for future designs, you may contact me directly.
Best Regards,
Ronald J. Rhodes
President
Conductor Analysis Technologies, Inc.
----------
> From: Craig McGlinchy <[log in to unmask]>
> To: [log in to unmask]
> Subject: [TN] Fine Line technology
> Date: Wednesday, September 02, 1998 5:11 PM
>
> Hi there,
>
> I am a new PCB designer, and as part of my training I have been asked
> to investigate the limitations (and why these exist), and effects on
> cost/yield etc of using fine line technology.
>
> I would really appreciate it if you could pass on any information you may
> have regarding the above topic. I have listed a few questions below that
> I feel outline the scope of what I am expected to find out.
>
> 1) What are your minimum track width/spacing capabilities, and what is
> the limiting factor?
> ie. If you state your minimum is 5mil, why is it 5 rather than 4mil?
> Is this limit due to imaging process, or is it the etching
process?
>
> 2) What about inner layers? Why are these different?
>
> 3) What about different types of boards, are these different? if so,
> why?
> eg, flexible, teflon etc
>
> 4) Why do you charge more, the finer the line width/spacing?
> ie. Why is 5/5 more expensive than 12/12?
>
> If you have any questions/comments, please don't hesitate to contact
> me.
>
> Best regards,
> Craig McGlinchy
> PCB Designer
> Tait Electronics Ltd
> Ph (64) 3 358-3399 extn 8509
> Fax (64) 3 358-0432
> email: [log in to unmask]
>
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