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September 1998

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Sender:
DesignerCouncil <[log in to unmask]>
Subject:
Re: FW: pcb design rules
From:
TOM HYBISKE <[log in to unmask]>
Date:
Fri, 18 Sep 1998 14:18:42 +0000
In-Reply-To:
<000e01bde327$a1a7cb80$7c6bb5cc@ken>
Reply-To:
"DesignerCouncil E-Mail Forum." <[log in to unmask]>, TOM HYBISKE <[log in to unmask]>
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text/plain (32 lines) 
> From: Ken Bown [mailto:[log in to unmask]]
> Sent: Friday, September 18, 1998 12:10 PM
> To: [log in to unmask]
> Subject: pcb design rules
>
>
> LOOKING FOR DEESIGN RULES FOT PCB LAND SPACING VS VOLTAGE  NEED TO APPLY 2KV
> BETWEEN LANDS AND CONNECTOR PINS.
> REGARDS, KEN BOWN
> DELTA V INSTRUMENTS
> RICHARDSON. TX
>
You can use the following guidelines:
0.00012 inch per volt for external layers
0.0001 inch per volt for internal layers

These are guidelines only! ZZZAP!
Tom Hybiske
General Atronics Corporation

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