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September 1998

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DesignerCouncil <[log in to unmask]>
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From:
"Cuomo, Bob" <[log in to unmask]>
Date:
Fri, 18 Sep 1998 10:57:30 -0700
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"DesignerCouncil E-Mail Forum." <[log in to unmask]>, "Cuomo, Bob" <[log in to unmask]>
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I believe you've got that reversed.  The track width determines the
current carrying capacity and therefore the temperature rise of the
track.  The voltage can ionize the space between tracks and break down,
causing arcing.

There are three situations to consider

1. Uncoated boards sea level through 10,000ft with voltages greater than
500: the minimum spacing is 0.0002 in/V.
2. Over 10,000ft with voltages greater than 500: the minimum spacing is
0.001 in/V.
3. Conformal coated boards at all altitudes with voltages greater than
500: the minimum spacing is 0.00012 in/V.

I got this from a "cheat sheet" I have from an IPC spec but for the life
of me don't know which spec it is.

> -----Original Message-----
> From: JoAnn Amerson [SMTP:[log in to unmask]]
> Sent: Friday, September 18, 1998 11:31 AM
> To:   [log in to unmask]
> Subject:      Re: [DC] FW: pcb design rules
>
> On 18 Sep 98, Ken Brown wrote:
>
> > LOOKING FOR DEESIGN RULES FOT PCB LAND SPACING VS VOLTAGE  NEED TO
> APPLY
> > 2KV BETWEEN LANDS AND CONNECTOR PINS.
>
> Hi Ken -
>
> You are trying to compare apples and oranges.  Voltage determines the
> track
> widths needed, current determines the spacing between traces, pins,
> etc.  At
> least I'm fairly certain about this answer.  I'm sure there will be
> better answers
> forthcoming.  :-)
>
> Jo
>
> JoAnn L. Amerson
> Design Librarian
> Red Lion Controls, Inc.
> E-mail: [log in to unmask]
> Voice: (717) 767-6961 ext 6308
>
>
> Thought for the day:
>   We should seize every opportunity to give encouragement.
>   Encouragement is oxygen to the soul.
>        -George M.Adams
>
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