At 06:24 PM 9/15/98 +0100, Derek Wynne wrote:
>I need to know the current carrying capacity of the following VIAS.>
>
>1.      0.6mm ring  0.4mm drill hole
>
>2.      1.0mm ring      0.6mm drill hole
>
>3.      1.4mm ring      1.0mm drill hole
>
>
>
>How many of the above would I need to carry
>
>
>
>a.      1A
>
>b.      1.5A
>
>c       5A
>
>With a standard ? plating thickness on a 5V digital board.

Unstated in the question is how much voltage drop or temperature rise are
acceptable in the via.

Standard copper plating thickness in holes might be not less than 25 um as
an average, and not less than 15 um anywhere. These figures are from a
purchase specification suggested by Preben Lund. If I read Lund correctly,
tin-lad plating over the copper requires a derating factor on the current
of 1.42. I have neglected this in some of the calculations below.

If the hole is unrelieved from a plane, or from a large trace, it may also
not realize the theoretical heat rise expected in a long trace of the same
effective diameter.

The resistance, R, in milliohms, of a trace can be calculated using the
formula

R = 0.0172 * L / A

Where L is the length in millimeters and A is the cross-section area in
square millimeters (Lund).

Temperature rise is more difficult to calculate; it is not linear; I use a
chart from the old MIL-STD-275C.

Anyway, an 0.6 mm hole has a circumference of 1.9 mm. So if this hole is in
a PCB which is standard 0.062 inch material, and the hole carries current
all the way through the board, we have a 1.9 mm trace which is 0.065 inch
long. The heat rise in a long trace which is 1.9 mm wide, 35 um thick [1 oz
copper] would be expected to be
about 10 degrees C at 3 amps, and 30 degrees C at 5 amps. 20 degree C
temperature rise is a normal limit. However, unless the traces to which the
vias terminate are themselves as thin as the via plating (unlikely), the
smallest via mentioned would probably handle the highest current mentioned,
because the barrel is so short and heat would be conducted away from the
via. On the other hand, I used a 1 oz copper figure (because it is the
thinnest copper thickness in the chart), instead of the approximately 50%
of that which would be the case at minimum material condition. The effect
of MMC is easiest to see by reducing, for calculation purposes, the trace
width proportionally, to 0.95 mm. This would give a 10 degree C rise at 2
amps and a 60 degree rise at 5 amps. With the derating factor of 1.42
mentioned above for tin-lead plating, we look at 7.1 amps rather than 5
amps, and the temperature rise from the chart is about 100 degrees. Don't
do it.

A 20 degree rise, after consider the derating factor, is expected at about
2 amps.

An 0.4 mm hole, tin/lead plated, would handle 1.5 amps with a current rise
of about 20 degrees.

A 1.0 mm hole, tin/lead plated, would handle 5 amps with a 20 degree
allowable rise.

The voltage drop in the via will also be relatively small because of how
short it is. It will, of course, be directly proportional to the current,
so, for 1 amp current, the voltage drop in millivolts will be equal to the
resistance in milliohms. For 0.015 mm thickness, 1.9 mm "width" (0.6 mm
via) 1.6 mm length, the formula gives 1 milliohm, corresponding to 1
millivolt drop.

The voltage drop is inversely proportional to the diameter of the hole,
other things being equal.

All these calculations are theoretical. But I have never heard of via
failure due to excessive current. Then again, I don't know of any example
where someone has tried to pump 5 amps through an 0.4 mil via. I would
expect it to fail.

The only reason I would think that one would try to use such a small via in
a power path would be on a multilayer board, where the power is being
communicated from one layer to another, and one needs the space on other
layers for traces. This is quite unusual.

[log in to unmask]
Abdulrahman Lomax
P.O. Box 423
Sonoma, CA 95476

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