DESIGNERCOUNCIL Archives

September 1998

DesignerCouncil@IPC.ORG

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DesignerCouncil <[log in to unmask]>
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Date:
Tue, 29 Sep 1998 07:29:41 -0700
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"DesignerCouncil E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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************************************************************************
*    This message was originated by automatic IPC Chat Session
*    Request Page (http://jefry.ipc.org/IPCchat/IPCchat_request.html)
************************************************************************

Nic De Roose  ([log in to unmask]) announces a Chat session with topic
"Lead-times deigning Printed Board Assembly".
The Chat session will be held on 09/29/98, at 02:35 P.M. GST
 (Please note the time zone - it might be different from yours)

Nic De Roose 's comments:
I would like to know what the average lead-time is for the design
of a relatively complex board.
The lead-time is to be expressed in weeks; starting from
1.Generation of detailed specs
2.Schematics/Simulation
3.Layout and routing
4.Prototyping
5.Test and validation
The board complexity is supposed to be comparable with
a PC motherboard just as reference.
Regards
Nic De Roose


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