Hi all,

I have been looking back at information on dielectric strength testing,
mainly from Ralph, and have a question.

I understand that the maximum which should be used for testing inner layer
tracks is 50 V/mil. I have a test which is carried out on tracks with 12
mil spacing where we apply 500 Vdc for 5 seconds. This test is carried out
twice on some tracks but is repeated twice more, once after assembly at our
customers end, and again at their customer's also.

My question is, if this test is repeated several times does this lead to a
greater likelihood of inducing a defect in an otherwise good PCB?

Any responses would be greatly appreciated.

Paul Gould

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