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August 1998

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Subject:
From:
Brad Vanderhoof <[log in to unmask]>
Reply To:
Date:
Thu, 20 Aug 1998 18:54:20 PDT
Content-Type:
text/plain
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text/plain (167 lines)
Regarding X-outs.
I won't accept them on low or high cost boards.
Additionally,
If the pwb fab house has a low yielding lot, I won't accept any of the boards.
On-site quality inspectors keep from facing morale dilemas when reporting yield information.

Brad

-----Original Message-----
From:   Aric parr [SMTP:[log in to unmask]]
Sent:   Thursday, August 20, 1998 4:52 AM
To:     [log in to unmask]
Subject:        Re: [TN] Assy: Questions about panel layout...

It costs more to deal with X-outs than to scrap the panels in most arrays.

Cost 1) They must be handled separately, or you will place parts on the
bad panels, and scrap all those parts, too.

Cost 2) Each location or combination of locations must be handled
separately to avoid stuffing the X-out. A program change is required to
skip each x-out.

Cost 3) When the X-out gets tested, the X-out becomes a reject. To
maintain accuracy in the QC system, the data must be manually adjusted.

Does this cost offset the cost of saying no X-outs? I won't accept them on
low cost boards.

ARIC PARR
Sr. Manufacturing Engineer
Eaton Corp
1400 S. Livernois
P. O. Box 5020
Rochester Hills, Mi 48308-5020
[log in to unmask]
248 608 7780
Fax: 248 656 2242
-------------
Original Text
From: C=US/A=INTERNET/DDA=ID/TechNet(a)IPC.ORG, on 8/19/98 2:44 PM:
To: Aric Parr@01635@Lectron_RH,
EatonWHQ@CorpMail@WHQCleveOH[C=US/A=INTERNET/DDA=ID/TechNet(a)IPC.ORG]

Steve,

Call me and let's talk about it

FNK

Frank N Kimmey
EM Designer
C&K Systems, Inc
916-353-5366
[log in to unmask]

> ----------
> From:         Stephen R. Gregory[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;[log in to unmask]
> Sent:         Wednesday, August 19, 1998 10:40 AM
> To:   [log in to unmask]
> Subject:      [TN] Assy: Questions about panel layout...
>
> Hi Everybody!
>
>      I know when you're trying to reduce PCB costs when panelizing,
> you need
> to work with your fab vendor when laying out a panel so your panel
> works with
> their standard panel sizes. But I've got a few general questions about
> board
> orientation within a panel, and board surface finish.
>
>      A basic description of the board is that it is going to be a
> consumer
> product for TV's. It's a long thin board about 1" X 11.5". At one end
> of the
> board there will be eight gold fingers. I'd like to have it laid-out
> in a
> 12-up panel so that I can triple-pick and place the boards in a even
> sequence,
> I have a Zevatech 750 which has three heads. My question about
> orientation is;
> does it make any difference in the fab plating process to have the
> individual
> PCB's all oriented the same way with the fingers all along one side in
> the
> panel, or does it make things easier or cheaper to alternate each PCB
> 180-degrees out from each other so that the gold fingers run down
> along both
> sides of the panel? (This is assuming that the rest of the PCB is
> going to be
> HASL'ed) OR, would it be cheaper to just have the whole panel nickel
> plated
> and flashed with gold and not use HASL?
>
> One last question; this is a 12-up panel, there's no fine pitch, and
> it'll be
> 2-layer. As a general rule, should you be able to expect 100% good
> boards in
> the panel? If not, what are the usual cost breaks for X-outs? Out of
> 12
> boards, I would like to see at the very most no more than 2 bad boards
> in a
> panel...will that drive the cost up more?
>
> Sorry about these basic questions, but I'm kinda' clueless about the
> PCB
> stuff...
>
> Thanks!
>
> -Steve Gregory-
>
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