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August 1998

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Subject:
From:
Ralph Hersey <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Mon, 17 Aug 1998 13:38:25 -0700
Content-Type:
text/plain
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text/plain (67 lines)
Michael Thiel wrote:

> > We have an application that requires a 800VDC differential between
> > top & bottom traces on a printed circuit board, at rather high
> > current levels. Will we have any long term reliability, or dielectric
> > breakdown problems using regular FR-4? Please recommend any specific
> > products that will assure satisfactory results.
> >
> > Thanks!
> >
> ################################################################

Clipped it all--Hi Michael--

Counter to Jim's reply, do not use material test voltages for dielectric strength for applications, unless
you want to ensure a high risk for failure.  You've got to remember high voltage material testing
(qualification) is a short duration test, as such it is not a good indicator of long-term application
life.  Be careful if you are using "thin" core or laminated material,  whit "thin" cores of approx. 0.25 mm
[0.1 inch] or less are tested, they test at far less voltage than the >28 kV per mm [700+ V / millinch]
that material testing in the range of 0.7 mm [0.03 inch] that is frequently used for laminate testing.

Derate the "rated" dielectric strength test voltages to less than 2 kV per mm [50 V/millinch] 1 kV per mm
is better for long-term high-reliability applications.  You might be successful at 4 kV/mm [100 V/millinch]
but an increased risk  in  failure rate.

Your query states 800 Vdc, is it pure dc???, no ac spikes or transients???

If you have any transients or "excursions" above aprox. 1.5 kV or greater, be vary careful about using
"commerial-off-the-shelf" laminated materials as many of these contain "acceptable sized voids" in the base
material.  About a year ago, I was asked to consult with an organization and their printed board
manufacturer, their problem was dielectric failure (electrical breakdown) at ~ 800 Vdc, with frequent
transients (spikes) of up to 1.5 kV and once-a-week transients (spikes) of up to 2.5 kV.  Of the several
failed assemblies, three of them had internal layer-to-layer shorts, only in the laminated core material,
and never in the printed board manufacturers "prepreg" layers.  The reason for this is thought to be due to
lamination practices; as the laminate manufacturers (in general) do not use vacuum lamination, and most
printed board manufacturers do, therefore laminate manufacturers have more of a propensity toward "voids"
in the base material, which under high voltage may "ionize" (corona) and lead to ultimate failure.

You may want to test you printed boards using "partial discharge high-voltage electrical test methods".
After you've established an acceptable level of partial discharge, then you can test your products.

Check the IPC's technet's archives for several very interesting discussions on "high-voltage" that address
the breakdown of (supposedly) solid dielectrics with voids and the effect of "Paschens Law".

Hope this helps--

--
Ralph,

Ralph Hersey & Associates
3885 Mills Way
Livermore, CA 94550-3319
PHN/FAX: 925.454.9805
e-mail: [log in to unmask]

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