You will need to be a little more specific on the problem you have on your
design for me to help. Its fair to say that I do not know of any other
application running chips of this size on the base of the board. If during
your design approval tests you had no problems them that should give you
confidence.

Look forward to getting more details. You can have zero defects on wave
soldered products provided the soldering process you are running is set up
correctly and the board is designed correctly.

Bob Willis
Process Engineering Consultant
Electronic Presentation Services
2 Fourth Avenue Chelmsford Essex CM1 4HA
England
Tel: (44) 01245 351502
Fax: (44) 01245 496123
Email: [log in to unmask]
Web Page: www.bobwillis.co.uk
-----Original Message-----
From: Paul Classic <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>; [log in to unmask]
<[log in to unmask]>; [log in to unmask] <[log in to unmask]>
Cc: [log in to unmask] <[log in to unmask]>
Date: 12 August 1998 07:52
Subject: RE: [TN] DFM guidelines


>Hi Peter
>Thanks God it's not a civil-aero , than I'd be worried .
>Something must be forcing you to the epoxy (I wouldn't) .
>And if you really insist on dragging SMD's through the wave :
>I am sure Bob (is on copy) will tell you where you stand .
>He's the author of the outrageous title :
>"Wavesoldering Surface Mount PCB's With Zero Defect" ,
>so blame him if you won't achieve the 100% pass :
>[log in to unmask]
>
>See you (wish you luck[you'll need more than that on class3])
>Paul Klasek
>http://www.resmed.com
>
>PS
>If you can not follow recommended manufacturers profile (may be
>difficult on wave) , you know you're in the reliability gray zone .
>The controlled cooling would help you on grain .
>Details with Werner Engelmaier (he may be on the road) :
>[log in to unmask]
>
>
>
>> ----------
>> From: mudbugz[SMTP:[log in to unmask]]
>> Sent: Wednesday, 12 August 1998 12:37
>> To: [log in to unmask]
>> Subject: [TN] DFM guidelines
>>
>> I have a customer who is transitioning from 100% through hole boards to
>> designing boards with smt components.
>>
>> We gave them our basic DFM guidelines and they have laid out 2 boards
>> following these guidelines.  When I saw the result of their first
>> pass, I
>> thought of two things.  1) we need to review our guidelines and 2) I
>> need
>> some advice from Technetters.
>>
>> The product is mil-aero building to IPC Class 3 using mil spec
>> components.
>>
>> The assemblies are all laid out for a process flow of
>> 1) reflow topside smt
>> 2) epoxy bottomside smt
>> 3) stuff thruhole
>> 4) wave solder
>>
>> I have 2 questions:
>>
>> 1)  They have placed smt resistors as large as 2512's and capacitors
>> up to
>> 1812 on the bottomside.  I recall reading about problems with wave
>> soldering large capacitors and having reliability problems.  Would
>> this
>> also apply to resistors?  What about the 1812 caps?
>>
>> 2)  They have also place 1206 resistors between the pins of .300 dips
>> on
>> the secondary side.  We had them orient the resistors parallel to the
>> wave
>> but unfortunately the dips are also oriented parallel to the wave (I
>> need
>> to check our DFM doc).  With this, they have positioned 6 1206's
>> between
>> the leads of a dip16 component and place 3 dip components in a row
>> with 3
>> 1206s between them.  ASCII art to follow.
>>
>> o - reps a dip lead
>>
>> [] - reps a 1206
>> []
>>
>> <-----  conveyor direction
>>
>> o  []  []  o  []
>> o  []  []  o  []
>> o          o
>> o  []  []  o  []    repeated 3 times in this direction
>> o  []  []  o  []
>> o          o
>> o  []  []  o  []
>> o  []  []  o  []
>>
>> Is anyone building anything like this successfully?  Volumes are less
>> than
>> 100/mo.
>>
>> Any input is appreciated.
>>
>> Peter Wong
>> [log in to unmask]
>>
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