EE TIMES has several articles in this weeks newspaper (8-17-98)
on high speed interconnects.
Go to the Signals section
Excelent reference material for leading edge designs.
Article titles:
-Designers hone interconnect smarts
-Interconnect modeling breaks new ground
-Designers eye interconnect issues
-Gbit serial lines unsnarl backplane
-GTLP raises backplane performance
-Wide conductors cut microstrip loss
-Speed aggravates board crosstalk
-Timing errors haunt interconnects
-Simulation saves signal integrity
Raymond Smith
Sr. PWB Designer
Tellium
Oceanport, N.J.
[log in to unmask]
################################################################
DesignerCouncil E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c
################################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body:
To subscribe: SUBSCRIBE DesignerCouncil <your full name>
To unsubscribe: SIGNOFF DesignerCouncil
################################################################
Please visit IPC's web site (http://www.ipc.org) "On-Line Services" section for additional information.
For technical support contact Hugo Scaramuzza at [log in to unmask] or 847-509-9700 ext.312
################################################################