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May 1998

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Subject:
Solder void acceptability
From:
Duane Briggs <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Tue, 19 May 1998 18:17:15 -0400
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IPC-610-B does not address voids inside solder joints so I'm requesting the
input of fellow practitioners.  Searching the archive turned up nothing on
this subject.  Soldering (both wave and reflow) sometimes results in voids
that can be x-ray imaged and verified by destructive testing.  Some of
these voids or combination of voids result in SMT heel fillets that are
less than 50% of the width of the lead or less than 50% hole fill.  Some
voids from reflow seem inevitable especially in J-leaded solder joints.
 Has anyone tried to quantify how much voiding is acceptable?  I would
appreciate all thoughtful responses.

Duane B
[log in to unmask]

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