Robert T. Moncada wrote:
>
> Technetters-
>
> Is there a formula for figuring current carrying capacity of
> vias?
>
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Hi Bob--
A couple of months back, I did a "long" attachment as a reply to a
similar inquiry on technet. I provided the background and method of
using the "ohms-per-square" method of determining the electrical
properties of conductive patterns.
Simply though, the following method will meet your needs.
The thermal rise above ambient design requirements in IPC-D-275, Figure
3-4, and IPC-D-6012, Figure 6-4 are based on a conductors
cross-sectional area (CCSA). Based on the thermal rise above ambient,
due to the power loss (heat) generated in a conductor. The design
charts are based on the thermal spreading resistance of the conductor,
base material and convective air flow (heat transfer).
What is need to extend these requirements to plated-through holes (PTH)
is to ensure the electrical resistance (CCSA) of the PTH is << or worst
case = the CCSA of the conductor. If the CCSA is the same for the PTH
and the conductor, then the "power loss" (I**2 R) will be the same, but
there might be a small increase in the local temperature due to the
differences in heat transfer to the base material and ambient. However,
for most applications this is not a problem.
Generalized Method:
1) Model/determine the "resistance" or CCSA of the conductor
interconnecting with the land.
2) Model/determine the "resistance" or CCSA of the PTH to the
interconnecting land.
3) Make sure the "resistance" or CCSA of the PTH is < the "resistance"
or CCSA of the conductor -- which if true means you've got a
conservative design. If not, then you've got localized heating, that
may be "thermally non-compliant" and possibly a reliability concern.
As an example -- let's assume the following conditions:
The conductor width (CW) is ~0.3 of the land diameter.
The hole diameter (HD) of a PTH is about 0.7 of the land diameter.
The hole aspect ratio (l/d) is 3:1
The nominal conductor thickness (CTnom) consists of 25 micrometer foil
and is pattern plated another 25 micrometers (1 millinch).
The PTH, Cu plating thickness (CTpth) is 25 micrometer (1 millinch)
The CCSA of the conductor entering the land CCSAcnd = CTnom * CW
The CCSA of the PTH hole is ~ = pi * HD * CTpth
A one-liner describing conductor resistance in "ohms per square", which
is the electrical resistance across opposite sides of a square of
uniform thickness; and for "squares of resistance" of different
thicknesses (of the same material resistivity), the resistance in "ohms
per square" is inversely proportional to thickness.
The sheet resistance of a conductor entering the PTH land will ~ 0.3
mohm per square for 50 micrometer thick Cu.
The PTH will have a sheet resistance of ~ 0.6 mohm for 25 micrometer
thick Cu.
The land (in theory) will evenly distribute the current uniformly around
the circumference of the hole. Therefore, with a printed board
thickness -to- HD of 3:1, there is ~ 1-square of CTpth from one land to
the other. (Why? you may ask. HDpth * pi / hole length (3 HD) ~= 1
(+/- 20%) but close enough for a "back-of-the-envelope" approximation)
The sheet resistance of the conductor entering the land is ~ 0.3 mohm,
and for the PTH is ~ 0.6 mohms; therefore, the resistance of the PTH is
about twice the CTnom resistance, and therefore will have an increased
thermal rise in comparison to surface conductors.
However, "signal" conductive patterns are seldom "sized" due to current
carrying capacity and thermal rise above ambient, and therefore it's not
a problem
Power, ground, and "high-current" signals where conductors are "sized"
per the design or regulatory charts, then you've got a problem. You
need to reduce the hole's aspect ratio, increase plating thickness, or
add additional PTH's (in parallel) to reduce localized interconnection
resistance -- CAUTION - be sure the design ensures uniform current
distribution in the paralleled PTH's.
Conductor (plating) thickness will be a critical design (and more-so a
manufacturing) parameter. In the transition of the IPC's "Performance"
spec's from the IPC-RB-276 to the IPC-6012, for Class 2 products, there
was a very subtle change in the CTpth from 25 micrometer avg. to 20
micrometer avg. So you'll need to evaluate PTH CTpth requirements to
reduce the risk of latent functional failures.
If you're doing "blind" or "microvias" then you'll need to model the via
using the "ohms-per-square" in order to approximate thermal rise
conditions due to the variations in Cu plating thickness in the via's.
I believe that's got it, hope it meets your needs.
If you need some further help on information please feel free to contact
me (probably best off technet) and I'll do what I can.
Ralph Hersey
Ralph Hersey & Associates
3885 Mills Way
Livermore, CA 94550-3319
PHN/FAX: 925.454.9805
e-mail: [log in to unmask]
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For the technical support contact Dmitriy Sklyar at [log in to unmask] or 847-509-9700 ext.311
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