I have a land pattern design for a 132 pin PQFP, 386EX chip.

The Z & G Land Pattern dimensions this device was layed out for
are inset by a total of 0.6mm, when compared to the specifications
outlined in the IPC-SM782 standard. In other words the pads need
to come out by a further 0.3mm each side to meet the same specs as
IPC.

This is a fine pitch device, 0.635mm spacing between pads.

Question 1: What effect would or could this have upon the assembly
            line? We use HAL finish. Ie. Could there be reliability
            problems with mounting the package?

Question 2: Does this FP device require a better surface than a
            HAL finish, say Flash Gold or Alpha level?

The reasons I am asking is because we are having boards comming in
with faults. The fine pitch devices seem to be causing the most
problems.

One symptom we are experiencing is some pads on components are shiny,
some are dull, even to the extent this would occur on the same package.
Also connectors are troublesome. Our production boards don't appear to
exibit the same problems, however, our assembly house confirm that they
only temperature profile production boards, not these prototype ones.

The particular board which is consistently causing trouble is a 6 layer
SMT, processor board. Could ground planes in internal layers, underneath
the devices cause heatsinking problems for HAL finished boards?

Any thoughts or comments are most welcome.

Regards,

Colin Weber

---------------------------------------------
Cad/Cam Specialist
Research and Development
Varian Australia P/L
679 Springvale Road, Mulgrave,
Victoria 3170, Australia.Varian OSI

ph +61 3 9566 1409 (Voice Mail)
ph +61 3 9560 7133
Fax +61 3 9560 7950
E-Mail [log in to unmask]
Internet Home Page http://www.osi.varian.com
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