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May 1998

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Subject:
From:
"Dieffenbacher, William C" <[log in to unmask]>
Reply To:
DesignerCouncil E-Mail Forum.
Date:
Thu, 21 May 1998 07:44:53 -0400
Content-Type:
text/plain
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text/plain (127 lines)
Another reason for tenting vias is to plug up holes that might trap
contaminants (i.e.. flux residue or moisture) during or after assembly.
These residues sometimes cannot be easily cleaned out of holes that are
beneath parts.  Tenting vias also covers conductor areas beneath parts with
a dielectric which prevents moisture from causing electromigration or
corrosion in areas where conformal coating materials will not be applied.

Bill Dieffenbacher

> ----------
> From:         Scott Buscomb[SMTP:[log in to unmask]]
> Reply To:     DesignerCouncil E-Mail Forum.;Scott Buscomb
> Sent:         Wednesday, May 20, 1998 4:25 PM
> To:   [log in to unmask]
> Subject:      [DC] Pass the Knowledge
>
> I am still not sure why vias need to be plugged and/or tented. If an LPI
> covers the via annular
> ring enough to prevent shorts without tenting the hole (mask is drawn into
> the hole), why is it
> important that the mask covers the hole? Someone please enlighten me.
> Thanks,
> Scott Buscomb
>
> Jim Dobbins wrote:
>
> > At 12:44 PM 5/20/98 -0500, Pat Paulson wrote:
> > >Our assembly house wants the vias under the BGA to be covered with
> solder
> > >mask therefore the bottom should be covered too.  This means these are
> not
> > >valid test points.
> > >
> > >What are other people doing to get around this problem.
> > >
> > >The pads for the 50 mil pitch bga part are 25 mils and the escape via
> is 28
> > >mils.
> > >
> > >Thanks again!
> > >Pat
> >
> > For proto's, The two shops we have been using recently (Hadco and
> Multek)
> > are plugging the vias in locations that we stipulate with an epoxy that
> > they screen
> > on after LPI and HASL to side one of the pcb.
> >
> > Our default routing via pad is 25 mil diam, our bga pad is
> > 28 mil diam. We have our tools setup for 20 mil default soldermask
> > openings (top & bottom) on the default routing vias and have the shops
> do
> > the epoxy via plug to only the vias in the bga footprint. This minimizes
> > difficulties for our pcb assembly partner in the bga mounting/soldering
> > portion
> > of their process and gives us good access to nets for debug during
> prototype
> > bring up. We do not generally have a problem with the epoxy covering the
> > exposed portion of the vias on the bottom side of the board under the
> bga
> > footprint. We are able to get scope and ohmmeter probe contact to these
> > points.
> >
> > For production ICT we use 3 different vias for ICT test points (probing
> > bottom side only) these are 35, 30 and 25 mil diam pads on the bottom
> and
> > all use 25 mil pads on top. We are using allegro and use allegro's test
> > point function to insert/substitute these test vias for our default
> routing
> > vias.
> > All test point vias have soldermask openings of 3 mils greater than the
> pad
> > diam on the bottom and 20 mil openings on top. We then have all vias
> > (default and test point) plugged from the top. Thus far, this has not
> > caused a problem
> > with probe contact. In the past, we experienced problems with trying to
> > plug topside openings of test vias with LPI soldermask. This approach
> left
> > a mask ring in the pth near the bottom of the board and caused problems
> > with intermittent ICT probe contact.
> >
> > -jim
> > [log in to unmask]
> >
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