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May 1998

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Subject:
From:
Greg Bordash <[log in to unmask]>
Reply To:
DesignerCouncil E-Mail Forum.
Date:
Tue, 12 May 1998 13:18:33 -0400
Content-Type:
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text/plain (138 lines)
>Greater Toronto Area IPC Designers Council Meeting
>    "The 1st and only Canadian Local Chapter"
>
>****              Meeting Announcement                 ****
>
>
>Date:           Thursday May 21, 1998
>
>Time:           From 6:15 pm sharp  until 8:00 pm.
>
>Location:      ATI Technologies Inc.
>                   75 Tiverton Court
>                   Markham, Ontario, Canada
>                   2nd floor meeting room. Follow the signs from reception.
>                   ( Note that you must sign-in at the front desk.)
>
>Directions:   FROM  Hwy 404 & Hwy 7
>
>                   Follow Hwy 7 East of Hwy 404 to Allstate Parkway. Turn
>left (North)
>                   ( Note that Allstate Parkway is 1st intersection East of
>Hwy 404.)
>                   Proceed on Allstate Parkway to Tiverton Court. Turn left
>(West)
>                   ( Note that Tiverton Court is the 2nd street on your left
>at the top of
>                    Allstate Parkway past the first stop sign.)
>                   Proceed to the end of Tiverton Court to the ATI building
>parking.
>                   **********************************************************
>********************
>
>
>                   FROM  Hwy 401 & Hwy 404( Don Valley Parkway )
>
>                   Follow Hwy 404 North to Hwy 7 East exit.
>                   Follow Hwy 7 East of Hwy 404 to Allstate Parkway. Turn
>left (North)
>                   ( Note that Allstate Parkway is 1st intersection East of
>Hwy 404.)
>                   Proceed on Allstate Parkway to Tiverton Court. Turn left
>(West)
>                   ( Note that Tiverton Court is the 2nd street on your left
>at the top of
>                    Allstate Parkway past the first stop sign.)
>                   Proceed to the end of Tiverton Court to the ATI building
>parking.
>                   **********************************************************
>********************
>
>
>Topics:        Chip Scale Packaging (CSP)
>                   IPC Design Certification
>                   Local chapter membership
>                   Future locations & programs.


>Chip Scale Packaging (CSP) is one of the newest innovations in electronics
>packaging technology.  CSP is an enabling technology which is giving
>semiconductor manufacturers the opportunity to provide customers with cost
>effective solutions to the problems associated with electronic circuit
>miniaturization.
>This session will touch on a number of topics of interest to physical
>designers who
>face the challenge of designing boards with ever-increasing densities and
>need to
>understand what CSP is and how to apply it.  The focus will be on specific
>techniques
>for laying out boards with CSP components, with a view to the applications,
>characteristics, and process engineering constraints associated with this
>technology.

>- Definition of CSP
>- Types of CSP packages available and who has them
>- Characteristics of CSPs
>- Layout considerations; ball pitch, pad definition, routing constraints,
via options, etc.
- Applications / roadmap
- Process considerations / constraints


>Guest speaker:  Mike Bondi
>
>About the Speaker;
>
Mike Bondi is a Senior Project Leader with Memory Products Development at
>Celestica Inc., in Toronto, Ontario.  He received his B.A.Sc. in Systems
>Design Engineering / Management Sciences Option in 1994 from the University
>of Waterloo.  Previous to joining Celestica, his experience included both
>electrical and physical design of PCBs for low frequency analog and digital
>applications, as well as high-speed digital designs and semiconductor layout.
>
>He has been involved in the design of multi-chip memory modules (MCMMs) at
>Celestica since 1995 and specializes in the areas of Flash memory products
for mobile applications and high-speed PCB design.  He developed Celestica's
>first PCMCIA ATA Flash Card, and recently designed the first Flash Miniature
>Card to
>use Chip Scale Packaging technology.  He has co-authored several papers on
>the use
>of CSP in memory product applications.
>

>Please RSVP   with Ignatious Chong, Glenn Rutherford or Greg Bordash.
>
>Hope to see you there !!
>
>Greg Bordash -     President, Greater Toronto Area IPC Designer Council
>(905)882-2600 x8370    [log in to unmask]
>Ignatious Chong -  Vice President, Greater Toronto Area IPC Designer Council
>(416)448-5048      [log in to unmask]
>Glenn Rutherford - Treasurer, Greater Toronto Area IPC Designer Council
>(905)843-1384      [log in to unmask]
>
>*****************************************************************************
**************
>
>Regards, Greg.

Gregory E. Bordash,
Senior Technologist PCB Design
ATI Technologies Inc.,
33 Commerce Valley Drive East,
Thornhill, Ontario, Canada, L3T 7N6
Phone:(905) 882-2600 ext: 8370,   Fax: (905) 882-9339
Email: [log in to unmask]

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