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May 1998

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"Eltek Ltd. - Process Engineering" <[log in to unmask]>
Date:
Wed, 20 May 1998 08:23:37 -0400
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"TechNet E-Mail Forum." <[log in to unmask]>, John Waite <[log in to unmask]>
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Hi Ed,
    I've typically taken the gerber data for one of my "nightmare" jobs and modified it.  I would
incorporate various drill sizes and adjust the lands for minimum annular ring to a shield area.
Put the test pattern on the largest panel you run, incorporate HCD and LCD areas opposing each
other (allows to check front to back close down rates/funneling), Isolate circuits around the
edge of the panel and in the center.  I would also suggest incorporating impedance test lines
randomly for Electrical evaluation as well as your cross sectioning evaluation.  I'm sure that
there may be a generic pattern from IPC, but I've found that it is better to go through the
"pain" of generating one that may be more closely associated with the type of work and plating
issues I deal with in my shop.  Hope this helps.... JOHN WAITE

Eltek Ltd. - Process Engineering wrote:

> Hi technetters ,
> We are trying to evaluate some alternatives for pattern plating line . Apart
> of hole sizes , panel thickness etc there is great importance of pattern on
> the board , that represents land areas , isolated condoctors , isolated
> holes etc . Does anyone has this kind of test patern ??
> Regards
> Edward Szpruch
> Eltek Ltd - Israel
> Tel  972 3 9395050
> Fax 972 3 9309581
> E-mail :  [log in to unmask]
>
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