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April 1998

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Subject:
From:
Ralph Hersey <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Fri, 3 Apr 1998 11:04:46 -0800
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Steve Collins wrote:
> 
> This message is pointed to those of you involved in RF circuitry I think.
> 
> The IPC-6012 specification for trace with tolerance of ±20% is coming under
> fire here. Typically what can most PCB fabricators hold for trace width
> tolerance regardless of what IPC says. How do other RF designers specify
> trace width tolerances in critical circuits.
> 
> Steve Collins
> PCB Design Supervisor
> 
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Hi Steve--

First -- the acceptability requirements in the IPC-6012 and IPC-A-600
(as well as most other manufacturing and acceptance documents) are
"default" requirements and "unless otherwise specified in the product
definition data" (PDD) (i.e. typically the master drawing or mfg. spec.)

Secondly -- becareful in interpreting the conductor width requirements:

The IPC-6012 & IPC-A-600 "conductor width" (CW) requirements are only
applicable for "reductions" in CW less than CWmin and are -20% for Class
2 & 3, and -30% for Class 1.  NOTE - CWmin is the minimum CW as
specified in the PDD or if not specified then CWmin is 80% of the
"nominal" CW width specified in the PDD.

"Increases" in conductor width is controlled by "conductor spacing" CS. 
CW can be increased by 20% of CS for Class 3 and by 30% for Class 1 &
2.  NOTE - if CSmin is not specifed in the PDD, then CSmin is 80% of the
"nominal" CS specified in the PDD for Class 3, and 70% of "nominal" for
Class 1 & 2.

Literal interpretation of the requirements means that for "close" CS
the  increase in CW could be very small; however, for "wide" CS  the
increase in CW could be substantial (ludicrous).  As an example, assume
CS is 25 mm in the PDD, then CW could be increased by 2.5 mm.  Then the
"unless otherwise specified" allowences kick in and this allows another
20% or 30% reduction in conductor spacing.

So if you need to limit CW to more -64% or -56% of the DWC (design width
of conductor) or to limit CW +64% or +49% of DSC (design spacing of
conductor) then like some of the other response have suggested, document
your design requirements in the PDD --- otherwise it's ludicrous.

Ralph



-- 
Ralph Hersey

Ralph Hersey & Associates
3885 Mills Way
Livermore, CA 94550-3319
PHN/FAX: 925.454.9805
e-mail: [log in to unmask]

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