Mark,
Along with the other responses to date, accept the following:
     1. For SOIC's you may need to experiment with solder thieves at the
trailing edge (i.e. say you have a 6 pin SOIC and the leading edge at wave
contact is at pins 1 and 4, the thieves would be located adjacent to pins 3
and 6) to minimize bridging.
     2. QFPs can be wave soldered by rotating the device 45 degrees to the
wave and adding solder thieves to three of the corners (the corner that
contacts the wave first does not require solder thieves) and the trailing
edge corner thieves need to be elongated.  Check a Philips Data Book for an
example of this configuration.
     3.  Regardless of the component type (a must for multilayer ceramic
chip caps), the maximum delta temperature from preheat to solder should not
exceed 120 degrees C.  I personally try to target this delta at 100 degrees
C maximum.  I also do not wave solder ceramic caps larger than 1206 and
have stated for new designs that the preferred size is 0805 (0603 cracked
more than 0805 under controlled evaluations).
     4. Be wary of your glue dots.  If you choose to use double dots for
chip devices, ensure that after the component is placed that a dam is
evident.  If a dam is not present, a stream of flux residue, solder, or
other contaminates can reside under the component and cause current leakage
and possible shorting.
Look at the archives on this subject (roughly 6 months ago we had a
discussion on this or it may have been on the SMTNet).

Any other questions feel free to contact me offline.

Steve Sauer
Sr. Electronics Mfg. Engineer
Hill-Rom Company Inc.
812-934-1655

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