Dear Technet,

        We'd like some clarification (interpretation) of the
        requirements noted in:

J-Std-001B      pg.27   paragraph 10.1.2.2 - Coating Coverage...
IPC-A-610B      pg.74   paragraph 7.1.2 - Coating Coverage...

d. Be free of voids, BUBBLES, or foreign material which EXPOSE
component conductors, printed wiring conductors (including ground
planes) or other conductors, and/or violate design electrical spacing.


        Does the word "expose" in (d.) above mean;

 - No voids, bubbles, or foreign material "over" the runs (that the
 bubbles may open over time due to temperature and pressure variations
 and "expose" the conductors)?

 - That voids, bubbles, or foreign materials indicate an absence of the
 minimum required thickness of conformal coating?

 - Or the literal meaning of "expose" - to leave bare, endanger?


        We have received some PWAs with conformal coating that have
        bubbles between and over conductor runs and around and on
        components.  The bubbles over the runs are not broken open (not
        literally exposing the conductor).  The coating when viewed
        with the unaided eye appears hazy due to the multitude of tiny
        bubbles throughout the coating.  There are larger bubbles and
        small bubbles between runs that when added together would
        violate the minimum spacing requirements.  As I mentioned
        before, the bubbles are of various size and numerous enough to
        make the coating appear porous (spongy looking) mostly tiny
        bubbles throughout.  We are required by contract to meet
        J-Std-001B class 3.

        We would appreciate your help in sorting through this confusion.

Thanks,

Dominick Scarano
Lockheed Martin
Mfg. Training

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