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April 1998

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Subject:
From:
Christopher Jorgensen <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 8 Apr 1998 08:52:28 -0500
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Mike,

The subsection table of contents for each section of IPC-TM-650 was just updated for
the latest update (March 1998) of IPC-TM-650. In the update of the tables of
contents, I removed the reference to Method 2.1.4, as well as the other 'planned for
future release' test methods that were mentioned in other table of contents pages of
IPC-TM-650.

Susan Mansilla, chair of the Test Methods Subcommittee (7-11), and I felt that the
'planned for future release' methods that were listed did nothing but cause
confusion. Those methods weren't even listed in my status of standardization for test
methods, which I update on a regular basis.

For a current listing of the test methods that are being worked on right now, I refer
you to http://www.ipc.org/html/framesetcatseg.html, which offers the most up to date
status of working test methods and IPC documents. This same listing can also be found
in each issue of the IPC Review.

If you can't access the information by either of the above means, please contact me
directly. I would be more than happy to provide you with the list or answer any more
of your questions.

Regards,

Chris

Chris Jorgensen
Project Manager
IPC
2215 Sanders Rd.
Northbrook, IL 60062-6135
-p- 847-509-9700 x.328
-f-  847-509-9798
[log in to unmask]
http://www.ipc.org

>>> Mike Johnson <[log in to unmask]> 04/07/98 09:09AM >>>
Greetings to all,
I have a question on the IPC-TM-650 test methods book. In section 2.1
visual, under 2.14 solder examination. This was printed as planned for
future release. Does anyone have any information on this subject?  The
actual question I am trying to answer is as follows. Is there a minimum
and maximum allowable solder coating thickness for surface mount pads?
Also is there a surface insulation resistance specification?  Thanks for
your time in advance.

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