Eddie,
Thanks for your questions.  I understand where you want to go with the
questions.  Allow me to give you some insight on the frustrations of trying to
answer the questions for myself and through research.

>
>  This is where I wanted to go......

The forest road is dark and deep, and I've miles to go before I sleep....

>
>  It would be nice to have resistances which are considered safe by the IPC
>  for different spacings. What are the acceptable levels for each of the
>  different IPC combs?

Yes it would.  Now, give me a definition of "safe".  Does safe mean no
corrosion and no metal migration?  I've seen many cases where these don't
occur, but have excessive electrical leakage causing failure.  Does safe mean
no corrosion, no metal migration, and no excessive electrical leakage?  OK, at
what humidity levels?  At what temperature levels? At what voltage levels?
Solder masked or not?  FR-4 or CEM laminate?  Further complicate this with the
question - is this for a high impedance application, or standard electronics,
high frequency or high speed digital work, etc.  Another question - are you
working with high solids rosin fluxes, water soluble fluxes, low solids
fluxes, synthetic activated fluxes (if you are Bll Kenyon)?  Each give
different SIR characteristics.  What might be safe for rosins might not be
safe for low solids.

SIR measurement involves a resistance reading on a materials SYSTEM, with many
factors.  Trying to get a SINGLE pass-fail level that is "safe" for each comb
pattern is not an easy task.  I suppose you could go the conservative route
and say 1 terohm minimum at 85C/85% RH, but you'll never get this level or it
would be prohibitively expensive and not "real world".  Much like if I asked
you to build an aircraft that would never crash (save).  You could probably do
it, but would be prohibitively expensive.

>
>  If I take the IPC-B-36 comb pattern, and reduce the number of traces, to
fit
>  in under the cavity of a perimeter BGA device, how would I establish a
level
>  of cleanliness?

In reducing the size of the comb, you reduce the sensitivity of the pattern to
pick up contamination.  It can still be used to detect deleterious materials
under a low standoff device, but will not be as sensitive as a larger comb.
Susan Mansilla stated it well that real world contamination is seldom
uniformly distributed and SIR failures usually come from a point source of
contamination.  Decreasing comb size decreases the chance of seeing such a
point source.

How clean is clean enough?  That is the $64,000 (or whatever that translates
to in pounds) question.  The IPC committees have been trying to answer this
one for a long time.  You will find as many opinions on this subject as you
will people to ask.  For now, if you are using SIR as your ONLY tool, which I
don't recommend, then the 100 megohm limit in J-STD-001 and J-STD-004 for the
B-24 and B-36 patterns, respectively, I have found to be a reasonable
discriminator between "clean" and "unclean".  If you want to be more
conservative, use the 500 megohm value.

>
>  If I have different patterns to IPC (ie for use with BGAs), how do I
correlate them to IPC standard combs?

In my opinion, you don't.  Theoretically, some specifications allow you to
relate two different geometry patterns using the ohms per square normalization
technique.  How to do this is found in IPC-9201, the SIR Handbook and IPC-
TR-467, mentioned recently by Jim Maguire.  This method ASSUMES that you have
a contaminant that is everywhere constant or consistent.  This is usually not
the case, in my experience.  I don't like to see pass-fail numbers adjusted
based on the ohms per square method, but it is an accepted practice in both
the Bellcore documents and IPC-J-STD-001B, Appendix D testing.

This is my particular windmill to tilt upon.....  (read Man of La Mancha)

>
>  Does the trace width have any influence on the values?

Do you mean the width of the conductors or the separation between traces.  If
you refer to the separation, then in my view, no.  I have seen comparable
resistance readings for parallel lines 6 mils apart and those 25 mils apart.
More a function of the material system and materials.  If you talk about the
thickness of the trace itself, you are usually only talking about a few
microamperes at most and typically nanoamperes or picoamperes.  I have done
SIR testing on 4 mil traces with no problems.  I would not expect trace width
to affect pass-fail levels.
>
>  If I just go ahead and obtain the values for IPC combs and home grown
>  designs, how do I establish a level of cleanliness?

Again, there are as many approaches to this as people to ask.  Ralph Hersey, a
few years ago when still gainfully employed at LLL, gave a presentation on how
the 100 megohm level logically related to engineering tolerances and practices
on high impedance devices.  Ralph, if your listening, I still want a copy of
that presentation.....

What I would recommend is to talk with your design people.  Find out what the
absolute maximum amount of leakage current they could sustain without the
circuit being adversely affected.  This will be lower for a high impedance
circuit than for standard CMOS logic.  Select a driving voltage that is either
operating voltage (5-12 Volts) or a voltage perhaps 10 times this level (to
accelerate electrochemical failures), say 50 volts, and convert to the
necessary minimum resistance you need.     If the maximum current you would
withstand was 1 nanoampere and your test voltage was 50 volts, your minimum
resistance would be 5E10 ohms or 50 gigohms.

Now select a temperature-humidity regime.  I would not test at less than 85%
RH.  Temperature is a toss up.  Startwith Bellcore conditions (35/90) and work
up (65/90, then 85/85).  Can you meet the minimum at all three?

Then get all of your arguments in line for the naysayers in house and in
industry that tell you that this lab test cannot accurately predict field
performance.

It is a very complex issue and one not easily answered.

Doug Pauls
CSL
Chairthing, SIR TG

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