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April 1998

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Subject:
From:
Per Viklund <[log in to unmask]>
Reply To:
DesignerCouncil E-Mail Forum.
Date:
Fri, 24 Apr 1998 13:23:35 +0200
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Hi Mirka,

I feel I could put in a few cents here.

I work for Dansk Data Elektronik and I was driving the Supermax E-CAD
system in the benchmark so I have some front line experience I guess..

Having been in the benchmark my self, I must agree to all your points!

In a way, you can say that the grading indicated that the tools
on the market today are probably closer to each other in what
they can do compared to how it was a few years ago.

On the other hand, I felt that many of the grading points
where just skimming on the surface of the functionality.
Example: Do you have push 'n shove editing? -Yes we have -One point!
Well, every body has that today but: will the editor conform to
DFM rules? will it follow high speed rules? is it intelligent or just
plain stupid?
This is just one example where an -as I see it, a very critical issue
in the graded systems, could have been graded to a much deeper level.
That would probably give a larger span in the grading results.

As a comparison, there was over 6 point at steak on the single feature
of being able to add design rules in a spread sheet.

-Now, don't missunderstand me: I feel that the people who organizes this
benchmark has done a tremendous job and it sure isn't easy to create
a good grading sheet. -And we have already declared that we will
participate the next time!

About the routing times:
I belive Pete Waddell is going to write a more in depth article
in the PCBD magazine -I guess the May issue.
Some info:
We were given a fixed placement.
The clock was started.
We where given a set of new design rules on the form:
 Negative layers: min annular ring 13 mils
 Plane clear board edge minimum 23 mils
  etcetera......
and off we went.
The board was to be routed on 6 signal layers and 2 negative planes
with split power and ground.
The idea with a fixed number of layers was to make sure that ALL the
participating systems should have a  fair chance of completing 100%
so that the results could be compared.
Well, the idea is swell but we ended up with a design that routed
100% is about 20-30 minutes. I belive we handed in all the data after
about 4h which then includes:
 setting up stacks and rules to match the new ruleset.
 route the design
 add testpoints
 generate the split power/ground planes
 run check
 generate production documents.

We were then allowed to replace the board ourselves and reduce layers
if we could. It turned out that it could be routed 100% in only 3
signal layers in fairly short time but the power and ground was such
that it really demanded 2 layers which would have given you a result
with 4 signal layers and 2 power planes. However, having done that,
the benchmark comitty said that they where not going to collect the
data for that run.

This means that this years benchmark was not so much of a router race
but more of a 'how long from data to board' benchmark which I feel
is also more relevant. Agree??

As for the production data goes, we are also a little puzzled.
As a vendor, I'm naturally VERY interested to know why some data
was rated poor so we can fix whatever it was and we have tried
to  make contact with the grader but failed so far. -Won't give up
though. (if you read this: please mail me!)

I would have liked the production data grades to have more comments.
For example, every vendor had a comment about that the IPC-D-356 netlist
was of poor grade -but nothing was said about why.
We had a comment about having used aperture macroes in X-gerber instead
of plain rectangles. The shop graded that poor though it's actually
a user wish since it allows you to correlate gerber data directly
with your padstack names in the design. I guess what I'm really
trying to say is that the picture is more complex than just some
crosses in a poor or good  form.
Having said that, I was REALLY surpriced to see that some of
the vendors handed in boards with such major boomers as:
  - missing connections!
  - short circuits in the split power planes!!
  - thousends of clearance violations!!!

Some errors are embarrasing and easily explained as
'us apps engineers are just not making real boards too often'
while the errors mentioned above really shouldn't happend with the check
routines you have in todays tools.

Gee, I could go on forever but everything got to end somewhere.
I belive that many of the people involved in the benchmark is on
this mailing list so perhaps we'll see some more comments.

Have a nice week end.

Per Viklund

  ++++++++++++++++++++++++++++++++++++++++++++++++++
  +   SUPERMAX E-CAD                               +
  +   -The best layout tool in the world?          +
  +   Read our High Speed Design Tutorial at:      +
  +   http://www.dde-eda.com                       +
  ++++++++++++++++++++++++++++++++++++++++++++++++++

Mirka Halas wrote:
>
> Hello all,
>          after following the thread on another day I looked at the
> results of the PCB bench mark and did not see much usefull information
> about
> any of the Cad Systems.
> According to the chart on Task/Grading there is not that much difference
> in what each system can do.
> I did not see any information on how many layers were on the finished
> board,
> how long did the routing take to what percentage of finish.
> What is the price of the system?
> The Board/Performance Data is evaluation of manufacturability, but what
> it means
> Signal layer poor or excellent?
> Sometimes it seems that you get so much information and yet
> not much sense in all of it.
>
> Hope your day is better than
> my
> Mirka
>
> --
> Mirka Halas <[log in to unmask]>
>
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