Reply to:   RE>[TN] Multiple Passes Through The Reflow Oven

Hi John,
I recommend the following article:
"Failure of thick board plated through vias with multiple assembly cycles -
the hidden BGA reliability threat" by Kevin T. Knaddle and Mitchell G. Ferrill
of IBM Endicott (Journal of SMT, October 1997).

Good luck.

Charles Elliott
NPI Process Engineering
Newbridge Networks

--------------------------------------
Date: 1998.03.17 9:58 AM

I understand that the number of times that a printed circuit board is
exposed to the reflow process must be kept to a minimum.  I have never
seen, however,  information regarding the maximum number of times that a
board can be reflowed while maintaining solder joint/component
integrity.

A common practice, at my work location, is to expose board assemblies to
the reflow process in order to remove large components as the boards
exit the oven, while the solder is still liquidous.

In order to stop the above practice, I need some data to prove that this
practice is detrimental to PCB quality.   Does anyone have reliability
data regarding excessive reflow operations?

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