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February 1998

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Subject:
From:
"Hill, Mike E." <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 25 Feb 1998 17:52:46 -0500
Content-Type:
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Background:  As chairman of the Electrical Test Task Force,  I am asking
for some inputs to help in the rewriting of  IPC-ET-652, "Guidelines and
Requirements for Electrical Testing of Unpopulated Printed Boards".
This document was first published in October 1990.  During the October
97 meeting in Washington, D.C., it was decided that a rewrite would be
appropriate.  Up until now there has not been any interest in changing
this specification.  IPC-ET-652 is referenced in IPC-6012,
"Qualification and Performance Specification for Rigid Printed Boards"
and is therefore widely used in the industry. Missing from the 1990
version are things like...testing buried resisters and capacitors, more
definition for High Pot testing, and finding potential latent defects.

This rewrite will start in Long Beach, California at the April EXPO
meeting.  To get a jump start on the rewrite the Task Force had three
questions they wanted inputs from a wide range of sources.   The three
questions are as follows:

1. What is the definition of a test point?   (This is important to
determine if you are meeting the requirement of "100% test")

Today the specification reads:  " Test Point: Any feature on the printed
board that is accessed by the test system".

2. What is the definition of 100% electrical test"?

 Today the definition reads as follows:  "100% continuity and isolation
electrical test is the confirmation that the actual electrical
interconnect of conductive features matches a proven reference source,
including but not limited to CAD/CAM digital data, master pattern
artwork or released drawings.  !00% electrical test SHALL consist of
probing every end of net feature and unless specified on the drawing
includes the following:
a.Plated alignment and mounting holes
b. Heat sink lands not solder masked
c. Shielding around the perimeter of the PWB
d. Single point networks.
e. Both sides of a feedthrough VIA."


3. What types of defects are being missed by electrical test today?


Thanks for you feedback and please come to the Meeting in California if
you have the energy.  If it's anything like the meetings in 1990 it
won't be boring!!!


Mike Hill
Quality Manager
Viasystems, Richmond Virginia

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