Richard,

I am in agreement with Fred.  What does the cross section of the
holes look like before assembly.  Is there low copper?  Is the copper near
the
top and bottom of the hole thicker than the middle?  If you can attach a
picture of the cross section to the email this would help us see what you
are seeing.

John Haman Jr.

----------
> Richard,
> -perhaps you could elaborate further - are you sure you mean a ring
> void? or are you seeing a barrel crack in the center of the hole?  Is
there
> anything else "unusual" about the plated barrel of the hole -  is the
copper
> thin in the problem area, etc.?  How about on the surface of the part -
are
> the pads lifting?
>
> Usually the greatest stress is near the surface of the part, and you might
> expect to see some innerconnect problems or cracks in the plated copper
> at the knees of the holes if you have a lot of Z-axis expansion trouble
> from undercured or low Tg material.   It's pretty unusual for a copper
bath
> to be so screwed up that the ductility goes completely away (leading to
> barrel cracks), but it does happen - but frequently the knees crack first
> (unless the plating is thin in the center of the hole, i.e. dogboning).
>
> Speaking as a fabricator, I don't know why you'd put thermals on some
> planes and not on others; maybe you can explain why!
>
> Regards,
> Fred J.
>
> >>> Richard G Smith <[log in to unmask]> 02/24/98 05:13pm >>>
>      Fellow Techies,
>
>      I need your help!!
>
>      Here's the situation. We have an eight layer PCB with four internal
>      planes. Layers 3 and 4 of the planes have thermally relieved vias,
>      layers 5 and 6 do not. The via size is .018 +.000 -.018 finished and
>      are tented with soldermask.
>
>      The problem is that ring voids occur sporadiclly on layers 5 and 6
>      (non-thermal ties) after multiple thermal excursions during assembly.
>      A microsection of the board has confirmed this.
>
>      I contend that the board was fabricated improperly using lower grade
>      FR-4 and in conjunction with other issues such as low ductility
copper
>      and no thermal ties caused this problem. I am a PCB Designer so I may
>      be biased.
>
>      The assembler is saying that this is purely a design issue based upon
>      the fact that no thermal ties were provided.
>
>      In all my resarch no one (including fab houses) has indicated that
>      this problem is related to the lack of a thermal.
>
>
>      Any insight would be greatly appreciated.
>
>      Rick
>
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