TECHNET Archives

February 1998

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Doug Jeffery <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Sat, 21 Feb 1998 05:08:00 -0600
Content-Type:
text/plain
Parts/Attachments:
text/plain (175 lines)
Jeff,

The number you are looking for is 1000 volts per mill.. this is a
reference number.. you can ask your board supplier to send the tech
data sheet for the laminate you are running and that will give you the
materials insulation characteristic..tested to a standard method..at 1
ply of 1080 (.0025 usually) you probably are yielding a thinner in a 1
ply sistuation may be even as low as .002 or .0018" depending on fill
and press setup..

Doug Jeffery

You wrote:
>
>I have a .062" thick, 10 layer PCB that I am working with.  My first =
>round of prototypes came back a bit thin at .052" thick.  Between each
=
>of the inner layers of copper is only one sheet of prepreg, .0025" =
>thick.  I have a couple of long runs that are on separate inner
layers, =
>but they run right on top of each other.  The runs are about 5" long,
=
>1oz. copper, .04" thick.  The only separation between these runs is =
>through the prepreg layer.  Usually, we do not have a problem with
doing =
>this, but we usually have more than one layer of prepreg between =
>conductor layers. =20
>
>My problem is this:  during testing of the assembly, somewhere during
=
>surge, eft, or isolation verification, a few of the runs that run on
top =
>of each other, but on different inner layers have shorted together =
>internally in the PCB.  I don't know if it was during surge, eft, or =
>isolation testing.  Is there a way to quantify, calculate, or is there
a =
>general rule of thumb for determining the isolation characteristics =
>between inner layers of a PCB?  We are ready to do a second production
=
>run of the board where the prepreg thickness between the inner layers
is =
>doubled compared to the first prototypes, but I would like to get a
good =
>feeling if it will pass my testing before we sign off to produce the =
>boards.  I would appreciate anyone's comments or insight.  I have
listed =
>some of the test requirements below:
>
>Surge Testing:  3kV peak voltage (IEC waveform of 50usec duration)
>EFT Testing: 2kV peak voltage (IEC waveform of 2.5kHz frequency)
>Isolation Testing: 2kV ACrms, 60Hz, no more than 1mA conduction, =
>sustained for at least 1 minute
>
>Thank you for your time,
>Jeff Fries
>Design Engineer
>Harmon Industries, Inc.
>[log in to unmask]
>
>------=_NextPart_000_000C_01BD3D6F.7548A040
>Content-Type: text/html;
>        charset="iso-8859-1"
>Content-Transfer-Encoding: quoted-printable
>
><!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN">
><HTML>
><HEAD>
>
><META content=3Dtext/html;charset=3Diso-8859-1 =
>http-equiv=3DContent-Type>
><META content=3D'"MSHTML 4.72.2106.6"' name=3DGENERATOR>
></HEAD>
><BODY bgColor=3D#d8d0c8>
><DIV><FONT color=3D#000000 face=3DArial size=3D2>I have a .062&quot; =
>thick, 10 layer=20
>PCB that I am working with.&nbsp; My first round of prototypes came
back =
>a bit=20
>thin at .052&quot; thick.&nbsp; Between each of the inner layers of =
>copper is=20
>only one sheet of prepreg, .0025&quot; thick.&nbsp; I have a couple of
=
>long runs=20
>that are on separate inner layers, but they run right on top of
each=20
>other.&nbsp; The runs are about 5&quot; long, 1oz. copper,
.04&quot;=20
>thick.&nbsp; The only separation between these runs is through the =
>prepreg=20
>layer.&nbsp; Usually, we do not have a problem with doing this, but we
=
>usually=20
>have more than one layer of prepreg between conductor layers.&nbsp;=20
></FONT></DIV>
><DIV><FONT color=3D#000000 face=3DArial size=3D2></FONT>&nbsp;</DIV>
><DIV><FONT face=3DArial size=3D2>My problem is this:&nbsp; during =
>testing of the=20
>assembly, somewhere during surge, eft, or isolation verification, a
few =
>of the=20
>runs that run on top of each other, but on different inner layers have
=
>shorted=20
>together internally in the PCB.&nbsp; I don't know if it was during =
>surge, eft,=20
>or isolation testing.&nbsp; Is there a way to quantify, calculate, or
is =
>there a=20
>general rule of thumb for determining the isolation characteristics =
>between=20
>inner layers of a PCB?&nbsp; We are ready to do a second production
run =
>of the=20
>board where the prepreg thickness between the inner layers is doubled
=
>compared=20
>to the first prototypes, but I would like to get a good feeling if it
=
>will pass=20
>my testing before we sign off to produce the boards.&nbsp; I would =
>appreciate=20
>anyone's comments or insight.&nbsp; I have listed some of the test =
>requirements=20
>below:</FONT></DIV>
><DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
><DIV><FONT face=3DArial size=3D2>Surge Testing:&nbsp; 3kV peak voltage
=
>(IEC waveform=20
>of 50usec duration)</FONT></DIV>
><DIV><FONT face=3DArial size=3D2>EFT Testing: 2kV peak voltage (IEC =
>waveform of=20
>2.5kHz frequency)</FONT></DIV>
><DIV><FONT face=3DArial size=3D2>Isolation Testing: 2kV ACrms, 60Hz,
no =
>more than=20
>1mA conduction, sustained for at least 1 minute</FONT></DIV>
><DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
><DIV><FONT face=3DArial size=3D2>Thank you for your time,</FONT></DIV>
><DIV><FONT face=3DArial size=3D2>Jeff Fries</FONT></DIV>
><DIV><FONT face=3DArial size=3D2>Design Engineer</FONT></DIV>
><DIV><FONT face=3DArial size=3D2>Harmon Industries, Inc.</FONT></DIV>
><DIV><FONT face=3DArial =
>size=3D2>[log in to unmask]</FONT></DIV></BODY></HTML>
>
>------=_NextPart_000_000C_01BD3D6F.7548A040--
>
>################################################################
>TechNet E-Mail Forum provided as a free service by IPC using LISTSERV
1.8c
>################################################################
>To subscribe/unsubscribe, send a message to [log in to unmask] with
following text in the body:
>To subscribe:   SUBSCRIBE TechNet <your full name>
>To unsubscribe:   SIGNOFF TechNet
>################################################################
>Please visit IPC web site (http://jefry.ipc.org/forum.htm) for
additional information.
>For the technical support contact Dmitriy Sklyar at [log in to unmask] or
847-509-9700 ext.311
>################################################################
>
>

################################################################
TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c
################################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body:
To subscribe:   SUBSCRIBE TechNet <your full name>
To unsubscribe:   SIGNOFF TechNet 
################################################################
Please visit IPC web site (http://jefry.ipc.org/forum.htm) for additional information.
For the technical support contact Dmitriy Sklyar at [log in to unmask] or 847-509-9700 ext.311
################################################################


ATOM RSS1 RSS2