Our specification is 0.010"/ inch. Like everyone else, our assembly sites and
subcontractors experience the yield problems associated with warpage in the
0.005"-0.010" range. We work on the product design and manufacturing process to
keep this impact to a minimum.
I would prefer to leave the specification where it is and work the product and
process issues than to tighten our specification, throw the issue at the PCB
manufacturer and invite cost adders.
Kelly Kovalovsky
IBM Printed Circuit Solutions Engineer
Email: [log in to unmask]
Phone 607-757-4595, FAX 607-757-4621
[log in to unmask] on 02-19-98 06:48:51 AM
Please respond to [log in to unmask] @ internet
To: [log in to unmask] @ internet
cc:
Subject: Re: [TN] PCB warpage -Reply
Matthew,
IPC 275 specs out a multilayer .060" thick board as having a flatness
requirement of 1% which equates to .010" / inch.
Most of the time we receive boards that are well within the spec and we
process them with no difficulty. When an occasional lot of boards are
received that are on the high side of the spec we experience all the
problems you described.
Do you specify a tighter tolerance with your pwb shop. Does this tighter
spec cause an increase in pwb cost. ( According to IPC to reduce the spec
to .5% or .005" / inch reduces yields.
I am curious as to what you and the majority of the industry is
specifying.
Thanks,
Dan Shea
Sr. Manufacturing Engineer
The Foxboro Company
Tel # 508-549-2410
Fax # 508-549-4379
Email: [log in to unmask]
-----Original Message-----
From: Matthew Park [SMTP:[log in to unmask]]
Sent: Wednesday, February 18, 1998 6:53 PM
To: [log in to unmask]
Subject: Re: [TN] PCB warpage -Reply
JIm,
By the look of your message, you must be a quality eng/mgr or
sales eng/mgr. No harm if i am wrong. Qual/'sales eng/mgr's
usually like to go by the book and process/mfg eng's like to go by
what work and what not work. To get to my points, IPC-275 Bow
& Twist spec should be in a permanent storage. Boards that
are closer to 0.01"/inch spec causes some problems in smt
manufacuring and th wavesolding.
They introduces printing registration inaccuracies, uneven
solderpaste depositions and solderpaste skips. They go thru
bumping rides during p/p placement cycles and off-placements
of plcc's, qfp's and bga's are visible. They wont transfer thru
edge conveyors without an operator assistence. Some chip
components get disloged due to the springness of boards and
slight vibrations. They cause more open solder joints.
They allow flooding of solder on comp side during
wavesoldering and prevents solder wetting on the highest area
of warped boards. It becomes more important to have flat
boards with advancement of finer qfp's and bga's.
Bow & Twist spec of 0.002"/inch or less is better suitable for SMT
assy. I know a lot of board fab shops won't guarantee with hasl
boards.
regards
Matthew Park
Automation Engineer
NII Norsat International Inc.
>>> Jim Mathis <[log in to unmask]> February 18, 1998 2:27
pm >>>
I spec'd out .01"/inch, also, which used to be the spec. IPC-275
section
5.2.5.2 now specs Bow & Twist in terms of percentages. If you
don't have a
copy of IPC-275, let me know and I'll fax you the appropriate
pages.
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