Rod Martens wrote:
>
>      Hi,
>      What are you specifically trying to stress?  The solder joint
>      connection or the traces in the substrate?  The solder joint
>      reliability is directly affected by the underfill adhesion. (orders of
>      magnitude greater if you have good underfill vs. no underfill)
>      Let me know if you want more info on flip chip reliability issues.
>      Rod Martens
>      Hewlett-Packard
>
> ______________________________ Reply Separator _________________________________
> Subject: [TN] Flip Chip
> Author:  Non-HP-eng ([log in to unmask]) at HP-ColSprings,mimegw4
> Date:    1/20/98 1:54 PM
>
> Hi All:
>
> Our company has been asked to design substrates for a flip chip.
>
> The traces on the ceramic (or polyimide) substrate will run from the
> solder ball landing
> pads out to a std edge connector format. We plan to lay our flipped chip
> with 100uM (+/-16uM) 63/37 eutectic balls on the ceramic landing pads
> and
> reflow it. The resulting assemblies called Test Coupons, will be plugged
> into the per position Burn-in Board edge connector sockets and submitted
> to
> a burn-in > test stress evaluation for Lot Acceptance Testing (LAT).
>
> Are there any specs or papers that we could reference to help us guide
> us into this venture.
> Any input from any body will be appreciated.
>

Hi:
We are actually stessing the device. We are working with a semiconductor
manufacturer, and they have a requirement to burn-in devices (die). So,
instead of using a regular package we will be creating a carrier
(substrate) to perform both the burn-in and the testing.

Thanks
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