TECHNET Archives

January 1998

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
"D. Rooke" <[log in to unmask]>
Reply To:
TechNet Mail Forum.
Date:
Wed, 21 Jan 1998 00:53:48 -0500
Content-Type:
text/plain
Parts/Attachments:
text/plain (133 lines)
Ed,

The issue of non-functional pads has a long history. I keep a personal
archive of Technet items and I have many entries for this topic dating back
to Feb 1996.

I would like to comment on the first two items that you address.

First, the elimination of non functional pads will reduce the likelyhood of
short circuits in the inner layers, this is logical. However, one needs to
be very careful of the impact of changing the potential failure modes.

The bad news is that there is a short that is detected and contained by
electrical testing and/or AOI. The good news is that it is contained in the
manufacturing process. If, let's say for the sake of argument, an epoxy spot
on the inner layer foil surface has prevented etching, causing a 'blob' that
connects to the adjascent circuit, HOWEVER the inner layer pad has been
removed such that the short that would be evident, is no longer detectable.
After drilling, is it not likely that a near short, or at least a dielectric
spacing violation, is likely shipped to the customer???  I'd rather contain
my problems and deal with the current issues, than ship a potential latent
problem to my customers.

Another potential problem with removal of non-functional pads, is that the
design community tends to omit no opportunity to place circuits wherever
there is space. At least these non-functional pads remind designers that
there is a drilled hole, with positional tolerance, in the vicinity of the
trace. (I actually have a customer that removed pads on a 50 mil pitch
connector in order to route a signal between the non-padded through holes.
The result is a 0.005 dielectric spacing from circuit edge to drilled hole
edge!!!!)

Secondly, I would like to provide some real-life experiences with regards to
non-functional pads and thermal abuse related defects. We still have,
unfortunately, some customers that reject for pad lifting after thermal
stress. In virtually every case, when non functional pads are removed I
always tend to find pad lifting, whereas when non-functional pads are added,
the problem literally disappears. It seems that these pads are NOT
non-functional after all. This is probably related to the presence of resin
in the zone that is no longer occupied by the copper pad that has been
removed. This could help explain the via hole problems as outlined by Alan.

I'll take those good 'ol non-functional pads any day.

Dave Rooke
Viasystems Canada
= = = = =
>Alan,
>
>I have read your response with great interest. Although I agree with logic
of more copper more stability, I am curious as to what impact has been
related to increase of  shorts between the non-functional pads and adjacent
circuits and planes. I have seen a tremendous reduction in spacing between
the required drilled hole wall and the adjacent conductive surfaces as a
result of the increase in densities. Adding a pad with sufficient annular
ring would reduce this spacing even more.
>
>Regarding the impact on stress, have you found the improvement primarily be
in the x and y axis? I would suspect that the impact of the added pads on
the coefficient expansion differential in the z axis would be minimal. Were
the failures you where referring to post separation?
>
>I find your conclusions on improved drill accuracy for the smaller diameter
drill really interesting. I have always understood that
>the amount of drill splay or wonder was created upon the initial impact of
the surface and directly affected by the feed and speed. Which is why the
entry foil is so important. Could you please provide me with any documented
references as to the effect of internal features on drill accuracy. I feel
I'm getting behind in some things!  Wow its tough to  keep up with all this
new stuff! Any help  on this matter would be greatly appreciated.
>
>Thanks
>
>Ed Cosper
>Director Quality Assurance and Engineering
>Graphic Electronics Inc.
>Tulsa, OK
>
>----------
>From:  Alan Cochrane[SMTP:[log in to unmask]]
>Sent:  Tuesday, January 20, 1998 1:24 PM
>To:  [log in to unmask]
>Subject:  Re: [TN] Dead Pad Removal
>
>To All,
>
>I think we can not overlook other aspects of having non-fuctional pads.
>
>1. With cores getting thinner in products today, the more reatained copper
>on the layer the better the dimensional stability will be.
>2. For x-section analysis it is far better to have a complete pad stack to
>verify registration.
>3. On high aspect ratio holes(>8:1) we need to look at the interconnect
>stress.  We have built a significant amount of 18 layer product around .105
>thick.  Initially without non-functional pads present.  Product was
>assembled and opens were detected in ICT test.  In ALL cases the opens were
>traced back to components or via holes that had interconnects only on
>layers 1/2 and 17/18.  The next revision product was built with non
>functional pads included and no defects were detected after assembly.  This
>was not an isolated occurance and was not dependant on resin system(high Tg
>materials minimize but do not omitt the condition).
>4. In our porducts the inclusion of non functional pads has shown to
>minimize the amount of drill splay on small holes(<.012)
>
>I am not sure of the parameters of the commisioned testing that is
>currently underway.  I hope this will address the higher aspect ratio
>problems that are out there.  It has taken us years to overcome the stigma
>of the last round robin test where a great deal of our customers were
>afraid(based on that report) to design product that violated the findings
>of that testing.
>
>The only negative that we have encountered with including non functional
>pads is, the increase in capacitance on some higher speed designs.  This
>needs to be modeled and accounted for prior to routing.
>
>Regards,
>
>Alan B. Cochrane
>Corporate Director of New Technology
>Multek Inc.
--- EOF ---

##############################################################
TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c
##############################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body:
To subscribe:   SUBSCRIBE TECHNET <your full name>
To unsubscribe:   SIGNOFF TECHNET
##############################################################
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information.
For the technical support contact Dmitriy Sklyar at [log in to unmask] or 847-509-9700 ext.311
##############################################################

ATOM RSS1 RSS2