Hi All:

Our company has been asked to design substrates for a flip chip.

The traces on the ceramic (or polyimide) substrate will run from the
solder ball landing
pads out to a std edge connector format. We plan to lay our flipped chip
with 100uM (+/-16uM) 63/37 eutectic balls on the ceramic landing pads
and
reflow it. The resulting assemblies called Test Coupons, will be plugged
into the per position Burn-in Board edge connector sockets and submitted
to
a burn-in > test stress evaluation for Lot Acceptance Testing (LAT).

Are there any specs or papers that we could reference to help us guide
us into this venture.
Any input from any body will be appreciated.

thanks
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     Mission Peak Services

   Engineering Department

        Visit us at:

  http://www.missionpeak.com
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