In your message you wrote:

>     I have a 4 layer design which includes significant areas of solid
>     plane on every layer.  Our design guidelines call for clearances
>     between the plane and any other conductor (trace or pad) of 0.015" on
>     outer layers and 0.012" on inner layers.  Clearance trace-trace,
>     trace-pad, and pad-pad is 0.008".  The design Engineer wants 0.008"
>     clearance between planes and other conductive features.  Can anyone
>     explain the  reason for the difference between clearance to planes and
>     to other features?  We're using 1 oz. copper on the inner layers and
>     0.5oz. (1.5oz finished) on the outers.  Thanks in advance for any
>     words of wisdom you can provide.
>
>     Paul Ziarek

I would imagine that this has to do with how much voltage is being put to
the plane areas.  With tighter tolerances you will have higher probability
of arcing.  This would apply mainly to a voltage plane.  Other reasonings I
can think of for the greater spacings on the outers is for when the board is
placed in wave solder, there would be less chance of bridging.

Continued Success...

Lyle

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