Mr. Gross: From your posting I'm not sure if you are talking about
boards with dissimilar metals such as Cu with selective Au or just plain fine
line Cu circuits that are being reduced in line width or etched away. In either
case the problem is the result of the microetch in the OSP process. There are
two solutions.
        1. Solsermask over the interface of the dissimilar metals or the Cu
cicuit that's being etched out.
        2. If masking is not possible, reduce the amount of time or chemical
aggressiveness of your microetch. Some of the early proposed needs by suppliers
for a heavy microetch were overstated. A 30-60sec. microetch using an acidic
peroxysulfate system will remove about 5-10 u". This should be sufficient to
provide a clean and oxide free surface to react with the OSP coating without
creating excessive galvanic etchout.We have found no differences in coating
thickness and/or solderability during assembly using this appraoch in place of a
heavy microetch.

                                                Regards
                                                        Michael Barmuta
                                                        Staff Engineer
                                                        Fluke Electronics
                                                        Everett Wa.
                                                        425-356-6076

On Mon, 12 Jan 1998 08:55:38 -0800 HGross1029 wrote:

> From: HGross1029 <[log in to unmask]>
> Date: Mon, 12 Jan 1998 08:55:38 -0800
> Subject: [TN] OSP & Galvanic Etch
> To: [log in to unmask]
>
> Has anyone had experience with a problem
> on a board with OSP coating as regards to
> lines being etched out due to galvanic action ?
> If this is a problem, what can be done to prevent
> it and what causes it if it does happen ?
> thanx...
>
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