DESIGNERCOUNCIL Archives

January 1998

DesignerCouncil@IPC.ORG

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Thu, 22 Jan 1998 08:22:05 -0800
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"DesignerCouncil Mail Forum." <[log in to unmask]>, Ken Barrett <[log in to unmask]>
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Ken Barrett <[log in to unmask]>
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This has more to do with our process rather than our test point size.
We use Cadence Allegro as our PWB CAD system.  Allegro has a routine
called "testprep" that goes around and selects probe points for ICT.
When testprep uses a via, we allow it to actually change the padstack
to a test point.  This provides the opening in the soldermask as well
as increase the pad size from 25 to 35 mils.  If you are wondering what
this does to the routing, again it is just a matter of process control.
Testprep is run after all the smt packages are "fanned out" (bonding
pads connected to a via), so there is practically no routing on the
board anyway.

But 50 mil pads for ICT???  Man, you gotta get your test people to
give up those 16penny nails and move into 80's.... it's the 90's
after all.

Ken Barrett


> From [log in to unmask] Thu Jan 22 04:35:23 1998
> From: "E.A. Speer" <[log in to unmask]>
> To: "[log in to unmask]" <[log in to unmask]>
> Subject: test point pads
> Date: Thu, 22 Jan 1998 07:36:18 -0500
> X-Priority: 3
> MIME-Version: 1.0
>
> Ken,
> This is very interesting to me as we are currently in battle with ICT on
> probe point pads.  They are insisting on 50 mil pads.  In your email you
> stated that you use 10 mil finished hole in a 25 mil pad.  Is this for
> production PWB's?   What kind of problems are you hearing about from
> ICT, if any?  Please expand on this for me.
> Thank you for your time.
>
>
>
>
> > E.A. Speer
> > Artwork Engineer
> > email: [log in to unmask]
> > Telephone: (770) 246-8684
> > Fax: (770) 246-8765
> >
> > American Megatrends, Inc.
> > 6145-F Northbelt Parkway
> > Norcross, GA  30071
> > Telephone: (770) 246-8600
> >
> >
> > http://www.ami.com
> >
> >

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