Having read November's CircuitTree, I seek the aid of few good, erudite
TechNetters.

Grant that I know nothing -- Please forgive my naive questions.

The problem with direct chip attachment is seemingly defined as not
having a known good die (KGD).

1)  When one is mounting a die on an interposer, would the interposer
not face the same dilemma?  In other words what does the interposer do
to accomodate the absence of a known good die that the PCB could not?
(One can see after attachment the features are scaled up for PCB
attachment, though.)

2) Where is the crux of the problem?  Is it assembly or
design/construction ability at the PCB stage?

Tie Me, Fly Me, Whip Me, Flame Me for Asking
Thanks,
J. Warhelere

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