TECHNET Archives

December 1997

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Ralph Hersey <[log in to unmask]>
Reply To:
Date:
Fri, 19 Dec 1997 00:24:59 -0800
Content-Type:
text/plain
Parts/Attachments:
text/plain (246 lines)
Jana Carraway wrote:
>
> If there are any designers out there, perhaps you can help me with a question.
>  My question(s) is: how do you calculate the current carrying capacity of a
> via?  I have calculated the area of a 6 mil via and a 4 mil trace to the via
> and the area of the via is about 100x that of the trace.  But, how do you
> calculate this with respect to a power layer?
>
> Any help is greatly appreciated.  Thank you
>
> Jana Carraway
> Maxtek Components Corporation
> Beaverton, Oregon
>
> ##############################################################


Hi Jana--

Simply stated, you need to compare the cross-sectional area of the via
to the conductor, then you may want to evaluate the "thermal-rise above
ambient" and you'll feel comfortable that for most practical
applications.  The via is not a serious electrical concern, except at
high frequencies it's capacitive, at very high frequencies it becomes
inductive, and with high pulsed currents it becomes an "energetic
material" like a fusible link (detonator).

I believe the "area" comparison that was conducted compared the
cross-sectional area of the conductor to the surface area of the PTH
via, this is not a valid comparison.  As is mentioned (way down in what
follows) you need to compare the cross-sectional area of the conductor
to the cross-sectional area of the PTH via (where the electrical current
flows).

The following is a way (IMO that I found to be very beneficial for
performing electrical calculations for printed board (PB) conductive
patterns) you can perform our own technical analysis:

The easiest way of doing these types of analysis is to use a resistance
technology called sheet resistance, and I've always wondered why the PBD
(printed board design) community has not adopted this method for
determining conductor resistance.

The following is not short, but it's pretty complete.

The following are the basic steps to determine sheet resistance for
materials that I used in an "Electrical Characteristics of Printed Board
Base Materials" workshop that I did for the IPC for about 6 years (maybe
I should dust it off and make it available again????)

Sheet resistance is the resistance of a "square" of material of a
specified and uniform thickness and the units of measure are "Ohms per
Square".

Sheet Resistance is determined for the "Volume Resistivity" of the
material, for copper that's about 1.7 microhm-cm, which is the
electrical resistance between opposite faces of a cube of copper.

The resistance model for a resistor is:

        R = k p L / A = k p L / W * T

Where   R is the resistance of the resistor
        k is a constant for units and other stuff
        p is "rho" which is the volume resistivity of the material in
          Ohm-cm
        L is the length of the resistor
        / is the symbol for division
        A is the cross-sectional area
        W is the width of the conductor
        T is the thickness of the conductor
        * is the symbol for multiplication
        All units need to be consistent or you must adjust "k" to
        compensate for variations in units

The simplified resistance model for copper would be:

        R = 1.7 uohm-cm L / W * T (where "u" represents micro)

Next some simple "combination" of resistor fundamentals:

    Seriesing  Resistors

        If you put "n" number of like valued resistors in series, the
        equivalent resistance is equal to n * R(resistance of resistor)

    Paralleling Resistors

        If you put "n" number of like valued resistors in parallel, the
        equivalent resistance is equal to R/n.  A simple example, two
        resistors in parallel provide two parallel paths for current to
        flow, and according to Ohms Law, for a single resistor E = I * R
        where E = the applied voltage across the resistor and I = the
        current through it.  In a parallel situation the voltage across
        the resistors is the same, therefore E = 2I * R', in order for
        this equation to balance, R' has got to = R/2.  A more general
        solution, if the number of resistors was "n", then E = nI * R',
        where R' = R/n.

    Series-Parallel Combination (simple example)

        Two resistors in series,  R+R = 2R = Rs
        Two resistors in parallel,  R/2
        Two seriesed resistors placed in parallel,  Rs/2 = 2R/2 = R,
        and a more generalized case would be Requivalent = nR/n

Now to relate this to "Volume Resistivity":

        Two 1 cm cubes of copper in series would 2p = 2 * 1.7 uOhm-cm,
        which results in a resistor of 3.4 uohms, now if we place two of
        these in parallel it becomes 3.4/2 uohms or 1.7 uohms.  Note:
        that as long as we keep the same numbers of "cubical resistors"
        in series and parallel, we form a "square", and the resistance
        is always equal to the Volume Resistivity of the material.  Also
        note, we only equally changed "L" and "W" (the length and width)
        of the "resistor", and therefore "T" (thickness) was a constant
        equal to 1 cm, so for any given resistor thickness of a material
        the resistance between opposite sides of any sized "square"
        resistor is constant and is expressed in "Ohms per Square" for a
        specified thickness (which in real world applications is a
        variable).

Determining "sheet resistance" from the material property "Volume
Resistivity"

        Going back to the model for a resistor R = k p L / (WT),
        if L = W, then we have a "square" and therefore R = p/T, with
        everything else being constant.

            Then R = p (Ohm-cm) / T (cm) = p/T ohms

        A PB example:

            35 um thick Cu foil [1 oz/sqft] = 0.0035 cm

            Rohms/sq = p / T = 1.7 uohm-cm / 0.0035 cm = 485.7 uohms/sq

            Other useful sheet resistances.

            18 um Cu [1/2 oz/sqft] =  971.4 uohms/sq ~= 1 mohm/sq
            25 um Cu [3/4 oz/sqft or 1 millinch]
                                = 647.6 ~= 700 uohms/sq
            35 um Cu [1 oz/sqft] = 485.7 ~= 500 uohms/sq
            35 um foil + 25 um plating = 283.3 ~= 300 uohms/sq
            70 um Cu [2 oz/sqft] = 242.8 ~= 250 uohms/sq
            105 um Cu [3 oz/sqft] = 161.9 uohms/sq

        Comment:  Sheet Resistivity should not be used because the sheet
        thickness is a variable depending on application, therefore,
        sheet resistance is more appropriate and sheet thickness must be
        specified or understood.  Examples: In hybrid (MCM-C)
        technologies, sheet thickness is generally (understood) to be
        25 um; in the integrated circuit technologies, sheet thickness
        may be in um, nm or Angstroms.

It's a useful tool:

    To determine the resistance of a conductor, determine the number of
    of squares in series (L/W) determine T, find the sheet resistance
    for "T", multiple the number of squares in series * sheet
    resistance.

        A conductor's T = 35 um, L = 150 mm, W = 0.1 mm, the number of
        "squares" = L/W = 150/0.1 = 1500 * sheet resistance = 1500 * 500
        uohms/sq = 7.5x10^5 uohms = 0.75 ohms.

    For "short-wide" (parallel paths) L/W < 1 and the resistance will
    reduce.

Now it's about time for technical reinforcement to the solution to your
question.

    Using the length of the hole as L, and the circumference of the
    hole (pi D) as the width (W) of the conductive pattern and the
    thickness of the (copper) in the plated-through hole (PTH).  So
    the "aspect" ratio in "squares" for a  PTH, = L / pi D ~= L / 3 * D

        You stated the hole dia. is 0.15 mm, I assume this is a "blind"
        via and the length (depth) of the via is < 0.25 mm, Aspect Ratio
        ~= 0.25 / (3 * 0.15) ~ 0.5 squares long.  If your plating
        thickness is 25 um, then the resistance of the PTH via is
        ~700 uohms/sq * 0.5 sq = 350 uohms.

        You stated the conductor entering the land/via is 0.1 mm wide,
        assuming 35 um thick conductor (thin foil + plating) the sheet
        resistance is ~ 500 uohms/sq., and for reasons to be developed,
        let's assume a conductor length the PTH via length of 0.25 mm.
        Therefore, the resistance of a 0.25 length of conductor,
        Rcl = 500 uohms  * (0.25/0.25) mm (aspect ratio of conductor)
        which results in Rcl = sheet resistance = 500 uohms.

    The thermal rise above ambient of a conductor is based on the heat
    transfer from a conductive pattern to the base material (conductive
    heat transfer), the "spreading" of the heat in the base material to
    both sides of the base material, and then some air flow (natural /
    forced convective) per unit length of conductor.  The thermal rise
    above ambient in IPC-D-275 (Table 3-4) is based on the thermal
    impedance of a conductive pattern and base material, and the
    "uniform" heat transfer per unit area to air (natural convection).
    For heat (electrical power) the relationship is W = I^2 * R
    (I squared R).

    In your example, the heat generated by the PTH via will be about
    70% heat generated by an equivalent length of conductive pattern.
    NOTE:  This assumes that the heat transfer from conductor-to-base
    material, from PTH via-to-base material, and there is no localized
    thermal build up due to the close placement of all of the conductive
    patterns.  All of which in the real-world are false assumptions.

In summary (and Doug Pauls will respond "it's about time")

   In general for most designs, PTH's have lower thermal impedance and
   electrical resistance that the conductors entering/leaving the PTH,
   so in general, they are not concern for 99+% of applications.

   I know this is too long, but I thought I might be of general interest
   to Technetter's and I suspect somebody will sent to the designer's
   net.

Hope this provides you with the background information you need; if not,
contact me directly and I'll provide more information.

Ralph

--
Ralph Hersey

Ralph Hersey & Associates
3885 Mills Way
Livermore, CA 94550-3319
PHN: 510.454.9805
FAX: 510.454.9805
e-mail: [log in to unmask]

##############################################################
TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c
##############################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body:
To subscribe:   SUBSCRIBE TECHNET <your full name>
To unsubscribe:   SIGNOFF TECHNET
##############################################################
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information.
For the technical support contact Dmitriy Sklyar at [log in to unmask] or 847-509-9700 ext.311
##############################################################


ATOM RSS1 RSS2