A few comments on your via fill problem.
        1. Why do you care that the vias. (not component holes) are filled
with solder.  Many test have shown that there is better reliability if they
are not filled.  For instance, BGA vias cannot be filled as they must be
covered with soldermask to assure that the reflow solder doesn't flow down
the hole.
        2. If the primary side pad is SM covered, then I can assure you that
there is some soldermask or residue of soldermask in some of the holes.  This
will not solder! and is very random.  Smaller holes will have more of this.
        3. As you point out, the amount of connection to each hole changes
the amount of heat required to flow solder up the hole.  Also, the smaller
holes with no lead in them has less chance of touching the wave for long
enough to heat the hole and cause solder to wick.  Also fluxing is more
difficult to get 100% coverage on small holes.

        So with all of this against you, why try to accomplish all hole fill
when a typical wave process at best produces a 250ppmj defect
rate in the best case.
        Our thrust for 3 years has been to design boards with no wave solder.
In the cases where we have been able to eliminate wave solder, the defect
rate at test and in the field has dropped to being only failed components!

        Just my opinion.
        [log in to unmask]

        -----Original Message-----
        From:   Joe Wackerman [SMTP:[log in to unmask]]
        Sent:   Monday, December 15, 1997 8:26 AM
        To:     [log in to unmask]
        Subject:        Re: [TN] filling vias!

        Ed- We have this very same problem. The wave process should fill
vias, but
        doesn't always. I have one particular board, one particular via that
won't
        fill (double sided, mixed technology). It apprears the trace is
sinking to
        a large part on the top side. We are changing our paste screen to add
        solder over the via before SM reflow. We are hoping this will improve
the
        situation. Joe

        At 07:12 AM 12/15/97 -0500, you wrote:
        >Here is a general question to start out the week:
        >
        >Should the wave solder process be required to fill all the vias of a
double
        >sided/plated thru board?  Why or why not?
        >
        >Is it a good practice to probe vias for the ICT test?  Why or why
not?
        >What is recommended?
        >
        >(Our boards are double-sided plated thru, but the annular ring of
the via
        >on the top side is covered with solder mask (not tented) and I am
having a
        >heck of a time filling all the vias (98% success rate). The ICT
probes vias
        >and we are having ICT failures due to unfilled vias and the probe
method.
        >The ICT probes are being switched to a larger tulip type head.  We
        >inherited this design!!  A lunch (and bragging rights) between ICT
and
        >myself are on the line!)
        >
        >Ed Holton
        >Hella Electronics
        >313-414-0944
        >
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        Joe Wackerman
        Sr. Mechanical Engineer
        Parker Hannifin
        Compumotor Division
        http://www.compumotor.com
        voice 707-584-2522
        FAX 707-584-8015
        e-mail [log in to unmask]

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