> Careful with filling vias in wave!  We inadvertently filled the vias
     > under a cavity down ASIC one time.  The solder that filled the vias
     > also contacted the ASIC lid.  We shorted several net nodes together.

     A low-tech version of this:  years ago I saw a soldered via under an
     axial aluminum electrolytic cap (not directly under, but close).  The
     solder had bumped up enough to melt a hole in the plastic sleeve, and
     the bump was intermittently shorting to the capacitor's aluminum case.
     Lots of fun to troubleshoot until I wiggled the part and got a clue.


     Can I add an extra question to this soldered/tented via issue?  I am
     working on a layout with both through-hole, and top and bottom SMD.
     Many topside nodes require that I drop a via so they can be tested.
     Unfortunately, the tightness of the layout (seems tight to me anyway)
     is only leaving me room to put some of these test point/vias under the
     QFP and SOICs.  Since it is bad to have soldered holes under parts, I
     follow our standard design practice of tenting those vias.  But only
     plugged from the top, with the bottom side left open to allow testing.

     The board house making my prototypes called to question this.  He
     warned that impurities could get trapped in the plugged hole, from
     both his processes and our wave solder, and threaten long term
     reliability of the via.  Can anyone confirm or add any information to
     this?  Can the risks of this be compared to that of leaving filled
     vias under SMD parts?  I am making the test engineer happy, but is
     there a real cost to reliability?

     Thanks in advance for any input.

     Ron James
     PCB Designer
     UT Electronic Controls
     Huntington, IN
     [log in to unmask]

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