Ed- We have this very same problem. The wave process should fill vias, but
doesn't always. I have one particular board, one particular via that won't
fill (double sided, mixed technology). It apprears the trace is sinking to
a large part on the top side. We are changing our paste screen to add
solder over the via before SM reflow. We are hoping this will improve the
situation. Joe

At 07:12 AM 12/15/97 -0500, you wrote:
>Here is a general question to start out the week:
>
>Should the wave solder process be required to fill all the vias of a double
>sided/plated thru board?  Why or why not?
>
>Is it a good practice to probe vias for the ICT test?  Why or why not?
>What is recommended?
>
>(Our boards are double-sided plated thru, but the annular ring of the via
>on the top side is covered with solder mask (not tented) and I am having a
>heck of a time filling all the vias (98% success rate). The ICT probes vias
>and we are having ICT failures due to unfilled vias and the probe method.
>The ICT probes are being switched to a larger tulip type head.  We
>inherited this design!!  A lunch (and bragging rights) between ICT and
>myself are on the line!)
>
>Ed Holton
>Hella Electronics
>313-414-0944
>
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Joe Wackerman
Sr. Mechanical Engineer
Parker Hannifin
Compumotor Division
http://www.compumotor.com
voice 707-584-2522
FAX 707-584-8015
e-mail [log in to unmask]

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